Wyniki wyszukiwania - BazTech

1

Low Complexity Stopping Rule for Turbo Decoding : the Max-log Criterion

Ouardi Aissa

Journal of Telecommunications and Information Technology

|

2024

|

nr 1

34--38

EN

This paper presents a new stopping criterion for turbo decoding. It is based on the selection of the maximum log-alphas calculated by the log-MAP algorithm. The sum of these maximum alphas is compared with a threshold value. Then, a decision on the end of decoding is taken. Simulation results show that the max-log criterion offers the same performance as the sum-alpha and sum-log criteria, while maintaining the same complexity level. The max-log criterion uses only the max operator to select maximum alphas and a summation. Therefore, the proposed criterion is faster and offers lower complexity.

2

Design of a Modified Interleaving Algorithm Based on Golden Section Theory Enhancing the Performance of Turbo Codes

Iftene Essedik, Ali-Pacha Adda, Abderrahmane Lahcene Hadj

Journal of Telecommunications and Information Technology

|

2022

|

nr 2

35--42

EN

This paper investigates the design of a modified matrix interleaving algorithm as a way to improve the performance of turbo codes. This proposed solution, known as the matrix-dithered golden (MDG) interleaver, utilizes the characteristics of a matrix interleaver combined with the golden section theory. The performance of the proposed interleaving method is compared with that of matrix (M), random (R), and dithered golden (DG) interleavers. The comparison is made in terms of bit error rate (BER), frame error rate (FER), computational complexity, and storage memory requirement. The turbo coded system is implemented and simulated using Matlab/Simulink software. Results of simulations performed both in the additive white Gaussian noise (AWGN) channel and the Rayleigh fading channel demonstrate the effectiveness of the proposed interleaver. The MDG interleaver is an effective replacement for random interleavers, as it improves BER and FER performance of the turbo code and is also capable of reducing the storage memory requirement without increasing the system’s complexity.

3

A Modiﬁed Approach to Punctured Product Polar Codes

Hanif Mohammad Abu, Vaﬁ Sina

Journal of Telecommunications and Information Technology

|

2019

|

nr 3

63--69

EN

A high-performance polar code introduced as a product polar code can be constructed by concatenating two short length polar codes. The punctured structure of this code was achieved by puncturing one of its constituent codes. The constructed polar code provided better performance than a single polar code in the error ﬂoor region. However, its performance in the waterfall region was not as good as that of single polar codes. This paper proposes a new puncturing algorithm for product codes constructed by two identical polar codes. Puncturing is conducted on both constituent codes, to ensure that the new code outperforms the previously punctured product polar and single polar codes. This is evident in both waterfall and error ﬂoor regions.

4

Efektywność widmowa PA-BICM-ID w kanale z selektywnymi zanikami Rayleigha

Krasicki M.

Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne

|

2018

|

nr 6

363--366, CD

PL

W artykule przedstawiono nowe wyniki badań jakości transmisji w kanale z zanikami selektywnymi Rayleigha przy użyciu modulacji PA-BICM-ID (Packet- Appended Bit-Interleaved Coded Modulation with Iterative Decoding) i zwielokrotnienia OFDM. Po raz pierwszy dla takiego kanału porównano wyniki efektywności widmowej systemów wykorzystujących, odpowiednio, PA-BICM-ID i BICM-ID. Stworzony model symulacyjny miał odzwierciedlać właściwości sieci WLAN, tak w zakresie modelu kanału, jak i struktury symbolu OFDM.

EN

The paper is to contribute some new results displaying the performance of OFDM-Aided Packet- Appended Bit-Interleaved Coded Modulation with Iterative Decoding over frequency-selective Rayleigh fading channel. It is the first time PA-BICM-ID is compared with BICM-ID in terms of spectral efficiency. The simulation setup instantiates a real-world WLAN network with its specific channel model, and OFDM symbol structure.

5

PA-BICM-ID z przeplotem składowych sygnału

Krasicki M.

Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne

|

2017

|

nr 6

319--322, CD

PL

W artykule przedstawiono nowy, rozbudowany model systemu z modulacją PA-BICM-ID (Packet- Appended Bit-Interleaved Coded Modulation with Iterative Decoding), uwzględniający przeplot składowych sygnału. W części eksperymentalnej zbadano wpływ kąta obrotu konstelacji 16-QAM na jakość transmisji i wykazano, że dzięki przeplotowi możliwe jest zwiększenie odporności systemu na zaniki.

EN

In this paper, a new, extended model of PABICM- ID (Packet-Appended Bit-Interleaved Coded Modulation with Iterative Decoding), incorporating coordinate interleaver/deinterleaver, is introduced. As an experimental part of the work, the impact of 16-QAM constellation rotation on transmission quality is focused. The obtained results prove that coordinate interleaving boosts systems’ resistance to fading.

6

Modulacja PA-BICM-ID – transmisja w kanale wielodrogowym z zanikami

Krasicki M.

Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne

|

2016

|

nr 6

197--200, CD

PL

Zaprezentowano sposób użycia techniki PA-BICM-ID (Packet Appended Bit-Interleaved Coded Modulation with Iterative Decoding) w systemie wykorzystującym zwielokrotnienie OFDM, transmitującym w kanale ze skorelowanymi w dziedzinie czasu i częstotliwości zanikami Rayleigha. Przeprowadzono badania symulacyjne efektywności widmowej systemu dla dwóch modeli kanału (o różnych wartościach średniokwadratowego rozrzutu opóźnień) i dwóch wartościowości modulacji.

EN

In this paper it is shown how to apply a current transmission scheme called Packet-Appended Bit-Interleaved Coded Modulation with Iterative Decoding (PA-BICM-ID) in an OFDM-aided system transmitting over a time- and frequency-correlated Rayleigh fading channel. The performance of a proposed solution is examined in terms of system spectral efficiency. Two channel models, characterized by different r.m.s. time delay spread, as well as two cases of modulation order are considered.

7

System WLAN z iteracyjnym dekodowaniem multisymboli OFDM

Kotrys R., Krasicki M., Remlein P., Stelter A., Szulakiewicz P.

Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne

|

2014

|

nr 8-9

738--740

PL

Zaproponowano zastosowanie kodowania, przeplotu i iteracyjnego dekodowania dla wielostrumieniowej transmisji OFDM, oddzielnie dla sygnału w każdym odstępie modulacji. Opisany schemat transmisji może być zastosowany w sieciach i systemach MIMO następnej generacji. Własności zaproponowanego sposobu transmisji w kanale Rayleigha i kanałach WLAN-owskich zbadano w drodze symulacji. Zaprezentowano i omówiono wybrane wyniki BER(SNR).

EN

This paper investigates the MIMO communication system in which encoding, interleaving and iterative decoding of multi-stream OFDM signal is done separately in each signaling interval. The proposed transmission scheme may be used in the next generation MIMO systems. Properties of the proposed method of transmission over the Rayleigh and WLAN channels have been tested by a simulation. The article presents and discusses selected results of BER(SNR).

8

Pipeline processing in low-density parity-check codes hardware decoder

Sułek W.

Bulletin of the Polish Academy of Sciences. Technical Sciences

|

2011

|

Vol. 59, nr 2

149-155

EN

Low-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation – and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we study the conditions for necessity of idle cycles and provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a parity check matrix optimization method to minimize the total number of required idle cycles and hence, maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties. Results, presented in the paper, show that the decoder throughput can be significantly increased with the proposed optimization method.

9

Konfigurowalny dekoder kodów LDPC implementowany w układzie FPGA

Sułek W.

Pomiary Automatyka Kontrola

|

2009

|

R. 55, nr 8

606-608

PL

Kody LDPC są jednymi z najlepszych znanych klas kodów nadmiarowych, służących do korekcji błędów w kanale telekomunikacyjnym. W niniejszej pracy zaprezentowano opisany w języku VHDL konfigurowalny dekoder podklasy kodów LDPC zorientowanych na efektywną sprzętową implementację. Możliwe jest dostosowanie dekodera dla dowolnego kodu LDPC ze zdefiniowanej podklasy, jak również konfiguracja pewnych parametrów dekodera decydujących o jego własnościach strukturalnych oraz własnościach korekcyjnych systemu. W artykule przedstawiono możliwości konfiguracji dekodera oraz wyniki implementacji: zasoby strukturalne oraz przepustowość dla kilku wybranych kodów.

EN

The group of Low-Density Parity-Check (LDPC) codes is one of the best known error correcting coding methods that are capable of achieving very low bit error rates at code rates approaching Shannon's channel capacity limit. The article concerns the configurable decoder for a subclass of LDPC codes that are implementation oriented. The decoder has a form of synthesizable VHDL description. It can be adjusted for decoding any code from defined subclass, called Architecture Aware LDPC (AA-LDPC). Configuration of some decoder parameters (message calculating algorithm, message wordlength) is possible as well. These parameters affect decoder structural properties and on the other hand - error correcting performance of the coding system. A number of modifications in the VHDL source code are required to adjust the decoder to the particular AA-LDPC code. These modifications can be made automatically by a software that has been created using Matlab tool. The user needs only to specify the parity check matrix that has architecture-aware structure as well as to specify other parameters of the decoder, such as: message wordlength, maximum number of iteration, the number of computing units (SISO) and the SISO message update (sub-optimal) algorithm. Based on these parameters, automatic generation of synthesizable VHDL description can be performed by the software tool that has been created. The decoder is implemented with the Xilinx VirtexII FPGA device. The simulation environment, making use of the hardware decoder is a base of the platform for fast simulation of the developed LDPC coding systems performance. In this paper we present mainly the decoder reconfiguration methods. Implementation results: structural resources and decoder throughput for a couple of different codes are presented as well.