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Event-driven firmware design with hardware handler scheduling on Cortex-M-based microcontroller

Mazur G.

Measurement Automation Monitoring

2018

Vol. 64, No. 1

20--22

The paper describes the concept and the design principles of a purely event-driven firmware for a Cortex-M core microcontroller used in an embedded system, based on hardware-scheduled event handling routines. The concept may be a practical alternative to the design paradigm based on an event loop or a real-time operating system, especially for not overly complex designs. When compared to an RTOS-based approach, the presented technique enables much shorter event response time and simpler synchronization of accesses to critical shared resources.

Implementacja kontrolera mikroprocesorowych układów transmisji równoległej w strukturach CPLD

Arnold K., Michalak S.

Pomiary Automatyka Kontrola

2012

R. 58, nr 7

635-637

W pracy przedstawiono możliwości zwiększania liczby wejść i wyjść równoległych w systemach mikroprocesorowych z wykorzystaniem programowalnych układów peryferyjnych. Wskazano ograniczenia w zakresie rozszerzania portów równoległych i zaproponowano rozwiązanie problemu multi-liniowej komunikacji mikrokontrolerów z otoczeniem przez sterowanie zewnętrznych specjalizowanych układów peryferyjnych z poziomu kontrolera CPLD, odpowiedzialnego za dekodowanie adresów wejścia/wyjścia i przyjmowanie zgłoszeń przerwań.

In this paper the possibility of increasing parallel inputs and outputs in microprocessor systems with a programmable peripheral interface (PPI) is presented. The requirements and restrictions associated with expanding parallel ports for microprocessors with internal bus and microprocessors with external access memory are described. The basic system with a central processor unit and parallel transmission device(s) is described (Fig. 1) and parallel interface modes for 82C55A PPI are shown (Figs. 2, 3). An example of multi-channel communication between a microcontroller and external units, with hardware CPLD controller and PPI devices, is given. The controller is responsible for input/output address decoding and interrupts receiving (Fig. 4). The external address/interrupt controller minimizes the time required by the microcomputer for interruption of the current program, servicing of the peripheral units, and resumption of the interrupted program. The basic requirements for programmable devices working as controllers in input/output parallel integrated subsystems are shown. The controller was implemented in one of XC9500XL family devices (Tab. 1). For each device from this family the I/Os are fully 5V (CMOS, TTL) tolerant even though the core power supply is 3.3 volts. In mixed (5V/3.3V/2.5V) systems a controller can work with low power supply microprocessors (Fig. 5). Use of this one programmable device gives us a chance for creating a flexible controller (Fig. 6) which can work with different kinds of 8-bit central units.