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Modelling and control of flexible manufacturing systems by means of interpreted Petri nets

Čapkovič František

Journal of Automation Mobile Robotics and Intelligent Systems

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2018

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Vol. 12, No. 4

3--10

EN

Because flexible manufacturing systems (FMS) are discrete event systems (DES), their modelling and control by means of Petri nets (PN) is widely used. While PN transitions are observable and controllable and PN places are measurable, place/transition PN (P/T PN) are suffcient for this aim. However, when some PN transitions are unobservable and/or uncontrollable and some places are non-measurable/unobservable, P/T PN are insufficient for modelling and especially for control. In such a case interpreted Petri nets (IPN) seem to be an appropriate replacement for P/T PN. In this paper a possibility of usage of IPN for FMS modelling and control is pointed out. Illustrative examples as well as the case study on a robotized assembly cell are introduced. By means of using timed PN (TPN) also the performance evaluation of the IPN model of controlled plant is accomplished whereby the simulation in Matlab.

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Weryfikacja modelowa hierarchicznej specyfikacji sterownika logicznego

Grobelna I., Grobelny M.

Pomiary Automatyka Kontrola

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2013

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R. 59, nr 8

796--798

PL

Specyfikacja zachowania projektowanego urządzenia powinna uwzględniać wszystkie elementy behawioralne. Z uwagi na złożoność projektowanych systemów szczególnie istotną rolę odgrywa możliwość dekompozycji. Z wykorzystaniem hierarchii można podzielić specyfikację na logiczne elementy połączone ze sobą na diagramach wyższego poziomu. W artykule przedstawiono zagadnienia związane z formalną weryfikacją hierarchicznych specyfikacji sterownika logicznego wyrażonych za pomocą interpretowanych sieci Petriego oraz diagramów aktywności języka UML.

EN

Specification of a designed logic controller should include all behavioral aspects. By complex systems design decomposition is especially valuable. Specification can be divided into parts using hierarchy. Logical elements are joined together at higher-level diagrams. The paper focuses on formal verification [1] of logic controller hierarchical specification by means of UML activity diagrams and interpreted Petri nets. Although hierarchy itself is presented in the considered specification techniques in different ways (complex activities by UML activity diagrams and macro-places/ macrotransitions by Petri nets), it is possible to use both techniques together in one project and to transform anytime one diagram into the another [5, 9, 10] (example in Figs. 1 and 2). In the transformation process, UML activity diagram actions correspond to Petri net transitions [7, 8]. Model checking [2, 3] of hierarchical specification can be performed step by step, e.g. by means of the NuSMV tool [11]. Rule-based specification (based on a Petri net) can be checked against behavioral properties [12, 13] expressed by temporal logic formulas [4]. Macroplaces can be verified separately (Fig. 3 considering local properties) and/or concurrently (Fig. 4, Fig. 5 considering mutual correlation and global properties). Next, the whole Petri net with macroplaces can be checked (Fig. 6). Sometimes it is convenient to verify a complete net (not hierarchical), like in [14]. Formal verification of specification can significantly increase its quality, and the support for hierarchy simplifies complex systems verification.

3

Zrównoleglanie algorytmów sterowania w systemach klasy PLC

Andrzejewski G., Skowroński Z.

Pomiary Automatyka Kontrola

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2006

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R. 52, nr 6 bis

62-64

PL

W artykule przedstawiono metodykę projektowania algorytmów sterowania, w których można wydzielić procesy współbieżne. Wskazano możliwość wykorzystania profesjonalnych narzędzi wspomagających projektowanie systemów cyfrowych, a w szczególności automatycznego translatora opisu HDL do interpretowanej sieci Petriego. Przedstawiono zarys algorytmu zrównoleglania procesów sekwencyjnych, a także metodę realizacji automatów skończonych i interpretowanych sieci Petriego, z wykorzystaniem języka LD (IEC 61131-3).

EN

A method for designing controller algorithms (with some concurrent processes) has been discussed. Particularly, this paper presents a usage of computer-aided design tools to solve synthesis problems of digital controllers and describes a method for transforming their specifications that are frequently given in sequential form - for example, processes in HDL into interpreted Petri nets. A paper also shows a parallelising process of control algorithms and a method of implementation of FSM and Petri nets with LD language (IEC 61131-3).