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1

Rearrangeability of 2×2 W-S-W Elastic Switching Fabrics with Two Connection Rate

Kabaciński W., Rajewski R., Al-Tameemi A.

Journal of Telecommunications and Information Technology

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2018

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nr 1

11--17

EN

The rearreangeable conditions for the 2×2 three-stage switching fabric of a W-S-W architecture for elastic optical switches are considered in this paper. Analogies between the switching fabric considered and the three-stage Clos network are shown. On the other hand, differences are also shown, which presented the modifications required in the control algorithm used in rearrangeable networks. The rearrangeable conditions and the control algorithm are presented and proved. Operation of the proposed control algorithm is shown based on a few examples. The required number of frequency slot units in interstage links of rearrangeable switching fabrics is much lower than in the strict-sense non-blocking switching fabrics characterized by the same parameters.

2

The Graph Theory General Position Problem on Some Interconnection Networks

Manuel P., Klavžar S.

Fundamenta Informaticae

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2018

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Vol. 163, nr 4

339--350

EN

Given a graph G, the (graph theory) general position problem is to find the maximum number of vertices such that no three vertices lie on a common geodesic. This graph invariant is called the general position number (gp-number for short) of G and denoted by gp(G). In this paper, the gp-number is determined for a large class of subgraphs of the infinite grid graph and for the infinite diagonal grid. To derive these results, we introduce monotone-geodesic labeling and prove a Monotone Geodesic Lemma that is in turn developed using the Erdös-Szekeres theorem on monotone sequences. The gp-number of the 3-dim infinite grid is bounded. Using isometric path covers, the gp-number is also determined for Beneš networks.

3

Sieć Banyana w implementacji sprzętowej dekodera LDPC

Sułek W.

Pomiary Automatyka Kontrola

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2011

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R. 57, nr 1

36-38

PL

Kody LDPC stanowią jedną z najnowocześniejszych metod kodowania dla celów korekcji błędów. Artykuł dotyczy sprzętowego dekodera podklasy kodów LDPC zorientowanych na implementację, który został opracowany w formie syntezowalnego opisu w języku VHDL. Jak pokazały wyniki syntezy, znaczną część powierzchni dekodera zajmuje moduł konfigurowalnej sieci połączeń. Sieć składa się z zestawu multiplekserów, które propagują dane z pamięci do jednostek obliczeniowych. Synteza behawioralnego opisu tego modułu daje niekorzystne wyniki. Dlatego też zaproponowano opis strukturalny z wykorzystaniem idei sieci Banyana oraz zestawu multiplekserów wyjściowych. Dzięki temu osiągnięto nawet kilkudziesięcioprocentową oszczędność powierzchni dekodera.

EN

Low-Density Parity-Check codes are one of the best modern error-correcting codes due to their excellent error-correcting performance and highly parallel decoding scheme. This paper deals with a hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The parameterizable decoder has been designed in the form of synthesizable VHDL description. Implementation in Xilinx FPGA devices achieves the throughput equal to nearly 100Mb/s. A significant part of the decoder area is occupied by the configurable interconnection network. The network consists of a set of multiplexers that propagate the data from the memory to computation units. The behavioral description of the interconnection network gives quite poor synthesis results: the decoder area is large and exponentially dependent on the number of inputs / outputs. Instead of the straightforward behavioral description, the switching network can be described structurally making use of ideas known from the theory of telecommunication switches: Benes or Banyan networks. In the paper there is presented in detail the interconnection network implementation based on the Banyan switch with additional multiplexer stage to enable non-power-of-2 numbers of outputs. Comparison of the synthesis results for the network based on the behavioral and Banyan structural description shows significant decrease in the decoder area in the second case.