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New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

Garbolino T.

International Journal of Electronics and Telecommunications

2015

Vol. 61, No. 1

67-75

The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built in blocks within a System-on-Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of the previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitive nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence.

Simple modeling approach for line impedance of on-chip CMOS interconnects

Ymeri H., Nauwelaers B., Maex K.

Journal of Technical Physics

2004

Vol. 45, no 1

71-77

Simple and accurate closed-form model enabling to calculate frequency-dependent distributed inductance and associated distributed series resistance per-unit-length of single on-chip interconnects on a lossy silicon substrate is presented. The closed-form formulas for the frequency-dependent series impedance parameters are obtained using a closed-form integration method and the vector magnetic potential equation. The proposed frequency-dependent inductance -L(omega) and resistance R(omega) per-unit-length formulas are shown to be in good agreement with the electromagnetic solutions.