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Design of prototype readout integrated circuit for time-of-arrival and time-over-threshold measurement for hybrid pixel X-ray detectors in 28 nm CMOS

Kadłubowski Łukasz A., Kmon Piotr

Przegląd Elektrotechniczny

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2022

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R. 98, nr 2

106--109

EN

This paper introduces the design and simulation results of a chip prototype dedicated for time-of-arrival (ToA) and time-over-threshold (ToT) measurement of X-ray photons. It consists of 8×4-pixel matrix with 50 μm pitch. Vernier time-to-digital converter with two ring oscillators is implemented in each pixel and aimed ToA resolution is on the order of tens of picoseconds. The chip may work in ToA/ToT mode or single photon counting mode. It is currently in fabrication.

PL

Artykuł przedstawia projekt i wyniki symulacji prototypowego scalonego układu odczytowego do pomiaru czasu uderzenia (ToA) oraz pośredniego pomiaru energii (ToT) fotonów promieniowania X. Układ zawiera matrycę 8×4 pikseli. Piksel ma wymiary 50 μm × 50 μm i zawiera przetwornik czas-cyfra w architekturze Verniera z dwoma oscylatorami pierścieniowymi. Planowana rozdzielczość pomiaru ToA jest rzędu dziesiątek pikosekund. Układ może pracować w trybie ToA/ToT lub w trybie zliczania pojedynczych fotonów. Aktualnie jest w produkcji.

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Trends in hybrid pixel detectors for X-ray imaging using deep submicron VLSI technology

Drozd A., Satława T.

Challenges of Modern Technology

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2014

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Vol. 5, no. 4

3--7

EN

The article covers the latest developments in pixel detectors used for X-ray imaging as well as the description of the practical solution – a multichannel integrated circuit dedicated to X-ray imaging. In general introduction a wide range of pixel detector applications is presented. The main part focuses on the challenges and new solutions for the field of X-ray imaging, including 3D integration, silicon-on-insulator and submicron technologies. Since minimization of a pixel size together with implementing more functionality are important issues in the detectors’ and integrated circuits’ design, the aspects of channel-to-channel uniformity and additional effects like charge sharing between pixels are taken into consideration. In the last section, the Authors present the application specific integrated circuit designed in 40 nm technology dedicated to X-ray detection and future prospects are discussed.

3

Readout Electronics for Pixel Detectors in Deep Submicron and 3D Technologies

Maj P., Szczygieł R., Gryboś P.

International Journal of Electronics and Telecommunications

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2011

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Vol. 57, No. 4

497-502

EN

We have designed, fabricated in 90 nm technology and tested a prototype ASIC for readout of semiconductor pixel detectors for X-ray imaging applications. The 4mm x 4mm readout IC is working in single photon counting mode and contains a pixel matrix of 1280 readout channels with dimensions of 100 µm × 100 µm each. We present the architecture, the measurement results of this IC and our conclusions. To make this chip more attractive for novel experiments, we need to further increase single pixel functionality and at the same time reduce the pixel area. This leads us to the 3D technology with at least two layers: analogue and digital and additionally the sensor layer. We present the concept of the 3D hybrid pixel chip design with small pixel size and the ability to build a dead-space free large area pixel matrix.