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Firmware development for the fibre-optic seismometer based on FOG

Kamiński Marek, Tylman Wojciech, Jabłoński Grzegorz, Kotas Rafał, Amrozik Piotr, Sakowicz Bartosz, Jaroszewicz Leszek R.

Opto-Electronics Review

2024

Vol. 32, No. 2

art. no. e150179

The main goal of the article is to present the concept of using a simulation environment when designing an advanced fibre-optic seismometer (FOS) using a field-programmable gate array (FPGA) computing system. The first part of the article presents the advanced requirements regarding the FOS principle of operation, as well as the measurement method using a closed-loop operation. The closed-loop control algorithm is developed using the high-level language C++ and then it is synthesised into an FPGA. The following part of the article describes the simulation environment developed to test the operation of the control algorithm. The environment includes a model of components of the measurement system, delays, and distortions in the signal processing path, and some of the measurement system surroundings. The article ends with a comparison of simulation data with measurements. The obtained results are consistent and prove correctness of the methodology adopted by the authors.

On implementation of FFT processor in XILINX FPGA using high-level synthesis

Smyk Robert, Czyżak Maciej

Poznan University of Technology Academic Journals. Electrical Engineering

2020

No. 104

17--33

The paper presents results of the high level synthesis of an 1024-point radix-2 FFT processors in Xilinx Vivado FPGA environment. The use of various directives controlling the synthesis process is examined. The results indicate that using the proper set of directives the latency of the processor can be reduced by 95% from about 35k for the default parameters to 1.5k cycles after optimizations.