Wyniki wyszukiwania - BazTech

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Zastosowanie dielektryków high-k w przyrządach mocy wytwarzanych w technologii węglika krzemu

Król K., Sochacki M., Kwietniewski N., Gierałtowska S., Wachnicki Ł.

Przegląd Elektrotechniczny

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2017

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R. 93, nr 8

106--109

PL

W artykule omówiono zalety zastosowania warstw dielektrycznych o wysokim współczynniku przenikalności elektrycznej osadzanych techniką ALD (ang. Atomic Layer Deposition) i praktyczne aspekty ich wykorzystania w przyrządach mocy typu MOSFET wytwarzanych w technologii węglika krzemu (SiC).

EN

This article describes the benefits of high-k dielectrics’ application in silicon carbide (SiC) technology aimed for production of power MOSFETs. The importance of the finding a new dielectric material for SiC MIS structures is explained and the main application problems are disscussed. The stacked dielectric layers of Al2O3/SiO2 and ZrO2/SiO2 manufactured by atomic layer deposition technique (ALD) on 4H-SiC substrates are then investigated by means of electrical methods useful in power device technology.

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Charge pumping characterization of MISFETs with SiO2/BaTiO3 as a gate stack

Firek P., Głuszko G., Łukasiak L., Szmidt J., Jakubowski A., Sochacki M.

Przegląd Elektrotechniczny

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2014

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R. 90, nr 9

26-28

EN

The results of charge pumping measurements of MISFETs with SiO2/BaTiO3 as a gate stack were presented and discussed. The characterization method was used for verification of thershold voltage and trap density values obtained by static current-voltage (I-V) measurements.

PL

W pracy zaprezentowano i przeanalizowano wyniki pomiarów tranzystorów MISFET wykorzystujących dwuwarstwowy dielektryk SiO2/BaTiO3. Pomiary wykonano przy użyciu metody pompowania ładunku. Stosowana metoda charakteryzacji posłużyła do weryfikacji wartości napięcia progowego tranzystora oraz gęstości pułapek powierzchniowych uzyskanych w oparciu o pomiar statycznych charakterystyk prądowonapięciowych (I-V) tranzystora.

3

Advances in flash memory devices

Ludwig C., Beug M. F., Küsters K. H.

Materials Science Poland

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2010

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Vol. 28, No. 1

105--115

EN

Fundamental challenges are discussed concerning the down-scaling of flash memory cells for mass storage applications. A general scaling issue for all various memory cell concepts is the structuring limit of conventional lithography. Therefore sub-lithographical structuring methods like e.g., double-patterning for future flash chips, have been evaluated. Another common scaling challenge of charge trapping (CT) and floating gate (FG) cells, the two future concurrent flash memory cell concepts, is the introduction of new materials such as high k dielectrics. Their implementation into CT and FG cells and the scaling related electrical issues of both cell concepts is also been discussed.

4

Charging Phenomena at the Interface Between High-k Dielectrics and SiOx Interlayers

Engström O., Raeissi B., Piscator J., Mitrovic I. Z., Hall S., Gottlob H. D. B., Schmidt M., Hurley P. K., Cherkaoui K.

Journal of Telecommunications and Information Technology

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2010

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nr 1

10-19

EN

The transition regions of GdSiO/SiOx and HfO2/ SiOx interfaces have been studied with the high-k layers deposited on silicon substrates. The existence of transition regions was verified by medium energy ion scattering (MEIS) data and transmission electron microscopy (TEM). From measurements of thermally stimulated current (TSC), electron states were found in the transition region of the HfO2/SiOx structures, exhibiting instability attributed to the flexible structural molecular network expected to surround the trap volumes. The investigations were focused especially on whether the trap states belong to an agglomeration consisting of a single charge polarity or of a dipole constellation. We found that flat-band voltage shifts of MOS structures, that reach constant values for increasing oxide thickness, cannot be taken as unique evidence for the existence of dipole layers.