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1

An Efficient Classification of Hyperspectral Remotely Sensed Data Using Support Vector Machine

Mahendra H. N., Mallikarjunaswamy S.

International Journal of Electronics and Telecommunications

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2022

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Vol. 68. No. 3

609--617

EN

This work present an efficient hardware architecture of Support Vector Machine (SVM) for the classification of Hyperspectral remotely sensed data using High Level Synthesis (HLS) method. The high classification time and power consumption in traditional classification of remotely sensed data is the main motivation for this work. Therefore presented work helps to classify the remotely sensed data in real-time and to take immediate action during the natural disaster. An embedded based SVM is designed and implemented on Zynq SoC for classification of hyperspectral images. The data set of remotely sensed data are tested on different platforms and the performance is compared with existing works. Novelty in our proposed work is extend the HLS based FPGA implantation to the onboard classification system in remote sensing. The experimental results for selected data set from different class shows that our architecture on Zynq 7000 implementation generates a delay of 11.26 μs and power consumption of 1.7 Watts, which is extremely better as compared to other Field Programmable Gate Array (FPGA) implementation using Hardware description Language (HDL) and Central Processing Unit (CPU) implementation.

2

FPGA implementation of H.264 CAVLC decoder using High-Level Synthesis

Cichoń S., Gorgoń M.

Image Processing & Communications

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2017

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Vol. 22, no. 2

21--26

EN

CONTEXT ADAPTIVE VARIABLE LENGTH CODING (CAVLC) is a method designed for coding residual pixel data after transform and quantization, in which different codes with variable length are chosen based on recently coded coefficients. Coded bitstream can be stored or transmitted. This method is optional in widely adopted H.264 video coding standard. The entire algorithm is a complex one, and also difficult to implement efficiently in FPGA, due to data dependency. When the complexity of the RTL implementation rises, it impacts the duration and costs of development. Therefore, usage of High Level Synthesis (HLS) may be beneficial with these types of projects. In this paper first known to authors implementation of CAVLC and Exp-Golomb decoders for H.264 intra decoder in Impulse C language will be presented and compared with other implementations. Proposed solution is able to decode more then 720p@40fps with FPGA module clock at 166MHz.

3

FPGA-based bandwidth selection for kernel density estimation using high level synthesis approach

Gramacki A., Sawerwain M., Gramacki J.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2016

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Vol. 64, nr 4

821--829

EN

Field-programmable gate arrays (FPGA) technology can offer significantly higher performance at much lower power consumption than is available from single and multicore CPUs and GPUs (graphics processing unit) in many computational problems. Unfortunately, the pure programming for FPGA using hardware description languages (HDL), like VHDL or Verilog, is a difficult and not-trivial task and is not intuitive for C/C++/Java programmers. To bring the gap between programming effectiveness and difficulty, the high level synthesis (HLS) approach is promoted by main FPGA vendors. Nowadays, time-intensive calculations are mainly performed on GPU/CPU architectures, but can also be successfully performed using HLS approach. In the paper we implement a bandwidth selection algorithm for kernel density estimation (KDE) using HLS and show techniques which were used to optimize the final FPGA implementation. We are also going to show that FPGA speedups, comparing to highly optimized CPU and GPU implementations, are quite substantial. Moreover, power consumption for FPGA devices is usually much less than typical power consumption of the present CPUs and GPUs.

4

Synteza i implementacja układu sterowania w strukturze FPGA opisanego językiem SFC zgodnego z IEC61131

Milik A., Pułka A.

Elektronika : konstrukcje, technologie, zastosowania

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2014

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Vol. 55, nr 12

17-20

PL

Artykuł przedstawia opracowany całościowy proces syntezy wielokontekstrowego sprzętowego układu sterowania implementowanego w strukturach FPGA. Dedykowana struktura sprzętowa pozwala na zdecydowane zredukowanie czasu przetwarzania w porównaniu z rozwiązaniami programowymi. Program podlegający syntezie jest opisany językiem SFC zgodnie z normą IEC61131-3. W procesie syntezy wykorzystano oryginalną grafową metodę reprezentacji postaci pośredniej programu sterowania. Metoda konstruowania postaci pośredniej zachowuje własności przetwarzania, ujawniając zadania równoległe. Opracowano również metodę odwzorowania technologicznego dla tablicowych układów FPGA. W celu porównania przedstawiono rezultaty implementacji opracowanej metody oraz bezpośredniego odwzorowania postaci grafowej.

EN

The paper presents the synthesis and implementation algorithms of multiple context logic controller implemented in a FPGA. A massively parallel hardware execution of control algorithms is utilized that significantly reduces the throughput time. The input program is written in the SFC according to the IEC61131-3 standard. An originally developed intermediate representation based on data flow graph has been used for processing. The graph building algorithm maintains sequential dependencies and reveals parallel tasks in program. Developed method of scheduling and mapping is dedicated for LUT based FPGA devices. The paper is concluded with exemplary implementation comparison of greedy direct mapping and developed FPGA architecture optimized method.

5

Synthesis and Implementation of Reconfigurable PLC on FPGA Platform

Milik A., Hrynkiewicz E.

International Journal of Electronics and Telecommunications

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2012

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Vol, 58, No. 1

85-94

EN

The paper presents a set of algorithms dedicated for synthesis of reconfigurable logic controllers implemented on FPGA platform and programmed according to IEC1131 and EN61131. The program is compiled to hardware structure with a massive parallel processing. The developed method automatically allocates resources and operations. It controls resource usage and operation timing. Using mixed concept of operation allocation that considers operation timing and forms combinatorial chains of operations number of execution cycles can be reduced. An example of logic functions, PID controller and mixed arithmetic and logic programming examples are considered. Introducing the automatic implementation method allows flexible implementing the control algorithms. The maximal possible parallelism (limited only by the algorithm dependencies and available resources) is introduced.

6

High level synthesis in EDA tool "Abelite"

Baranov S.

Electronics and Telecommunications Quarterly

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2009

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Vol. 55, No 2

123-156

EN

The paper presents the first description of methods and algorithms realized in experimental EDA tool Abelite. High level synthesis, implemented in this tool is based on Algorithmic State machine (ASM) transformations (composition, minimization, extraction, etc.), special algorithms for Data Path and Control Unit design and a very fast optimizing synthesis of FSM and combinational circuits with hardly any constraints on the number of inputs, outputs and states. Design tools supporting this methodology allow very fast to implement, check and estimate many possible design versions, to find an optimized decision of the design problem and to simplify the verification problem for digital systems.