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EN
In this paper a new Delta Sigma Fractional N synthesizer architecture is presented. The synthesizer achieves low fractional spurs and quantization noise, which relaxes the trade-off between PLL bandwidth and phase noise. The proposed architecture is based on two delay lines, which are used to compensate the phase error resulting from fractional synthesis. Additionally, dedicated control and calibration circuitry is described. The synthesizer has been implemented in standard 130 nm CMOS technology, occupies 0.1S4 mm² silicon area and dissipates 3.6 mW of power from 1.2 V supply. Measurements show that the presented architecture achieves 30 dB phase noise reduction in comparison with a standard Delta Sigma Fractional N synthesizer. The integrated rms jitter is 2.76 ps and worst case fractional spur is -52 dBc.
2
Content available remote The DDS Synthesizer (for FPGA Platform) for the Purpose of Research and Education
EN
The paper concerns the construction scheme of Direct Digital Synthesis (DDS) generator based on widely developed Field Programmable Gate Arrays (FPGA) technology. Firstly, the division of all generators is presented regarding the fact whether they generate sinusoidal or non-sinusoidal signals and whether the they have positive or negative feedback. Next chapter concerns how to generate frequency directly and indirectly synthesis and how to integrate these types of sytheses into the hybrid one. According to the blueprint, DDS generator if fully digital, which facilitates the control enabling to change almost at will the oscillation while the system works. Next chapters contain the conclusions and some proposals regarding practical application. DDS synthesizer has been made in accordance to the assumptions of the project, which was confirmed in practice. Control program enables us to fuse some measuring systems together into one, which facilitates simultaneous gathering of the data from several devices. Hence, the overall efficiency rises and the costs of carried out experiments are reduced. In the case of foreigners, it will be supplied by editors.
EN
The paper mainly introduces the new signal generator circuit of industrial frequency power based on XC2C64A, which focus all digital circuit in a CPLD chip, making simple structure and convenient debugging. And the general diagram, design idea, the benchmark waveform signal oscillating circuit, frequency synthesis circuit, phase synthesis circuit and D/A transformation circuit are given in the paper. The phase and frequency of the circuits are simulated.
PL
Zaprezentowano nową koncepcję genertatora sygnałów o częstotliwości przemysłowej wykorzystujący syntezę częstotliwości i fazy oraz przetwornik cyfrowo-analogowy. Układ bazuje na obwodzie XC2C64A.
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