Wyniki wyszukiwania - BazTech

Ograniczanie wyników

Znaleziono wyników: 2

Liczba wyników na stronie

Wyniki wyszukiwania

Wyszukiwano:
w słowach kluczowych: fotodioda lawinowa

Sortuj według:

Ogranicz wyniki do:

Investigation of HgCdTe avalanche photodiodes for HOT condition

Manyk Tetiana, Sobieski Jan, Matuszelański Kacper, Rutkowski Jarosław, Martyniuk Piotr

Bulletin of the Polish Academy of Sciences. Technical Sciences

2024

Vol. 72, nr 3

art. no. e149173

The performance of long-wave infrared (LWIR) x = 0.22 HgCdTe avalanche photodiodes (APDs) was presented. The dark currentvoltage characteristics at temperatures 200 K, 230 K, and 300 K were measured and numerically simulated. Theoretical modeling was performed by the numerical Apsys platform (Crosslight). The effects of the tunneling currents and impact ionization in HgCdTe APDs were calculated. Dark currents exhibit peculiar features which were observed experimentally. The proper agreement between the theoretical and experimental characteristics allowed the determination that the material parameters of the absorber were reached. The effect of the multiplication layer profile on the detector characteristics was observed but was found to be insignificant.

Design of a Hold-off Time Control Circuit for Geiger-mode Avalanche Photodiodes

Deng S., Morrison A. P. A. P.

International Journal of Microelectronics and Computer Science

2012

Vol. 3, nr 2

53-59

A high-resolution hold-off time control circuit for Geiger-mode avalanche photodiodes (GM-APDs) that enables linear changes to the hold-off time from several nanoseconds to microseconds is presented. The resolution of the hold-off time can be varied from nanoseconds to tens of nanoseconds with a range up to microseconds to cater for a variety of GM-APDs. This circuit allows setting of the optimal 'afterpulse-free' hold-off time for any GM-APD through digital inputs or additional signal processing circuitry. With this circuit, the APD is automatically reset following the end of the hold-off period that further simplifies the end-user's control. A layout of this circuit is designed using a conventional 0.15 μm complementary metal oxide semiconductor (CMOS) process, resulting a area of 95 μm x 55 μm which makes it suitable for use with APD arrays.