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2 Journal of Telecommunications and Information Technology

2 2010

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The Effect of High Temperature Annealing on Fluorine Distribution Profile and Electro-Physical Properties of Thin Gate Oxide Fluorinated by Silicon Dioxide RIE in CF4 Plasma

Kalisz M., Głuszko G., Beck R. B.

Journal of Telecommunications and Information Technology

2010

nr 1

25-28

This study describes the effects of high temperature annealing performed on structures fluorinated during initial silicon dioxide reactive ion etching (RIE) process in CF4 plasma prior to the plasma enhanced chemical vapour deposition (PECVD) of the final oxide. The obtained results show that fluorine incorporated at the PECVD oxide/Si interface during RIE is very stable even at high temperatures. Application of fluorination and high temperature annealing during oxide layer fabrication significantly improved the properties of the interface (Ditmb decreased), as well as those of the bulk of the oxide layer (Qeff decreased). The integrity of the oxide (higher Vbd ) and its uniformity (Vbd distribution) are also improved.

Novel Method of Improving Electrical Properties of Thin PECVD Oxide Films by Fluorination of Silicon Surface Region by RIE in RF CF4 Plasma

Kalisz M., Głuszko G., Beck R. B.

Journal of Telecommunications and Information Technology

2010

nr 1

20-24

This study describes a novel technique to form good quality low temperature oxide (< 350 C degree). Low temperature oxide was formed by N2O + SiH4:N2 plasma in a plasma enhanced chemical vapour deposition (PECVD) system on the silicon surface reactively etched in CF4 plasma (RIE - reactive ion etching). The fabricated oxide demonstrated excellent (for low temperature dielectric formation process) currentvoltage (I-V) characteristics, such as: low leakage current, high breakdown voltage and good reliability. Experimental results indicate that the proposed method of fluorine incorporation into the SiO2/Si inteface improves electrical parameters of MOS structures.