Wyniki wyszukiwania - BazTech

1

Novel architecture for floating point accumulator with cancelation error detection

Jamro E., Dąbrowska-Boruch A., Russek P., Wielgosz M., Wiatr K.

Bulletin of the Polish Academy of Sciences. Technical Sciences

|

2018

|

Vol. 66, nr 5

579-587

EN

A floating point accumulator cannot be obtained straightforwardly due to its pipeline architecture and feedback loop. Therefore, an essential part of the proposed floating point accumulator is a critical accumulation loop which is limited to an integer adder and 16-bit shifter only. The proposed accumulator detects a catastrophic cancellation which occurs e.g. when two similar numbers are subtracted. Additionally, modules with reduced hardware resources for rough error evaluation are proposed. The proposed architecture does not comply with the IEEE-754 floating point standard but it guarantees that a correct result, with an arbitrarily defined number of significant bits, is obtained. The proposed calculation philosophy focuses on the desired result error rather than on calculation precision as such.

2

Hardware implementation of hyperbolic tangent and sigmoid activation functions

Hajduk Z.

Bulletin of the Polish Academy of Sciences. Technical Sciences

|

2018

|

Vol. 66, nr 5

563--577

EN

This paper presents the high accuracy hardware implementation of the hyperbolic tangent and sigmoid activation functions for artificial neural networks. A kind of a direct implementation of the functions in a few different versions is proposed and investigated both by software and hardware modeling. A single precision floating point arithmetic is applied. Apart from conventional design style with hardware description language coding, high level synthesis design techniques with the Matlab HDL coder and Xilinx Vivado HLS have also been investigated.

3

Application of modular computing technology to number normalization in floating point arithmetic

Selianinau M.

Scientific Issues of Jan Długosz University in Częstochowa. Mathematics

|

2015

|

Vol. 20

57--67

EN

In the present paper, we deal with the methodology of mantissa normalization on the basis of parallel algorithmic structures of modular arithmetic. The use of interval-modular form and basic integral characteristics of modular code is fundamental for construction of floating-point modular computing arithmetic. The proposed method of mantissa normalization in the minimal redundant modular number system is based on the parallel algorithm of multiplication by constant with overflow check.

4

FPGA implementations of low precision floating point multiply-accumulate

Amaricai A., Boncalo O., Sicoe O

International Journal of Microelectronics and Computer Science

|

2013

|

Vol. 4, nr 4

159--163

EN

Floating point (FP) multiply-accumulate (MAC) represents one of the most important operations in a wide range of applications, such as DSP, multimedia or graphic processing. This paper presents a FP MAC half precision (16-bit) FPGA implementation. The main contribution of this work is represented by the utilization of modern FPGA DSP block for performing both mantissa multiplication and mantissa accumulation. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on one of the multiplicand, and, a left shift for the other. This results in efficient DSP usage; thus both cost savings and higher performance (high working frequencies and low latencies) are targeted for MAC operations.

5

Zmiennoprzecinkowa jednostka arytmetyczna dla sprzętowej maszyny wirtualnej

Hajduk Z.

Pomiary Automatyka Kontrola

|

2011

|

R. 57, nr 1

82-85

PL

W artykule omówiono, opracowaną dla struktur FPGA, implementację układów realizujących podstawowe operacje arytmetyki zmiennoprzecinkowej. Implementacja charakteryzuje się pewnym kompromisem pomiędzy zapotrzebowaniem na zasoby logiczne układu programowalnego a szybkością realizacji operacji arytmetycznych określoną przez liczbę taktów zegara niezbędną do wykonania operacji. Wspomniane układy zostały wykorzystane jako zasadnicze komponenty zmiennoprzecinkowej jednostki arytmetycznej przeznaczonej dla sprzętowej maszyny wirtualnej. Maszyna ta, implementowana w układach FPGA, jest specjalizowanym mikrokontrolerem wykonującym pośredni kod wykonywalny generowany przez kompilator środowiska inżynierskiego CPDev, przeznaczonego do projektowania oprogramowania sterowników przemysłowych. Wykonane testy wydajności maszyny sprzętowej wyposażonej w zmiennoprzecinkową jednostkę arytmetyczną wskazują, że jest ona średnio kilkadziesiąt razy szybsza od dotychczas istniejących realizacji programowych, wykorzystujących popularne mikrokontrolery AVR i ARM.

EN

Under the CPDev (Control Program Developer) engineering environment, programs written in one of the languages defined in the IEC 61131-3 standard are compiled into the universal intermediate code executed on the side of programmable controllers by the virtual machines [9]. There are software implemented virtual machines, dedicated for the platform with popular AVR and ARM microcontrollers, and also there is a recently developed hardware virtual machine implemented using FPGA devices [2]. The hardware virtual machine, which in fact is a specialized microcontroller described in the Verilog Hardware Description Language [3], is several dozen times faster then its software counterparts [2]. But the main drawback of the existing hardware virtual machine is a lack of the ability of executing the floating point computations. The paper presents an architecture of the floating point arithmetic unit accomplishing basic floating point operation, designed for the hardware virtual machine. There are quite a lot of publications concerning FPGA implementation of the floating point arithmetic, for instance [6, 7, 8, 10, 11]. In this paper the realization of basic float-ing point operation, balanced between logic resources requirements and speed of computing (defined by the number of clock cycles necessary to end up a floating point operation), is presented. Figs. 1 and 2 show a simplified micro-architecture of the single precision (according to IEEE 754-1985 standard [5]) floating point multiplier and adder. A floating point divider has roughly the same structure as the multiplier - it differs in states functions performed by some blocks. A few different realizations of the multiplier and adder unit were designed - the details are presented in Tabs. 1 and 3. The general trend is as follows: a shorter clock cycle necessary to execute the operation needs more logic resources of FPGA. A floating point unit for the hardware virtual machine was designed based on the floating point multiplier, divider and adder blocks. Apart from the mentioned above basic floating point operation, the floating point unit also performs operations like: comparison and relation (equals, not equals, more than, more than or equal etc.), absolute value, negation, integer value to floating point value conversion, floating point to integer conversion (rounding, truncating) and some functions fetched from IEC 61131-3 standard like MIN, MAX, LIMIT. To compare performance of the hardware virtual machine equipped with the floating point unit and its software counterparts, the Whetstone based benchmark [1] was written in ST language. The test results are given in Tab. 4. The hardware virtual machine (implemented using Xilinx Spartan 3-AN FPGA XC3S1400AN-4FGG676) is several times faster than the software one implemented on AVR and ARM microcontrollers, and even a little bit faster than the PC based virtual machine (under .NET environment).

6

Numerical stability of the Richardson second order method

Smoktunowicz A., Wróbel I.

Demonstratio Mathematica

|

2005

|

Vol. 38, nr 1

255--263

EN

In this paper we study numerical properties of the Richardson second order method (RS) for solving a linear system Ax = b, where A € Rnxn is infinitysymmetric and positive definite. We consider the standard model of floating point arithmetic (cf. [6], [7], [11]). We prove that the RS-algorithm is numerically stable. This means that the algorithm computes approximations xk to the exact solution x* = A-1b such that the error limfk||xk - x*ll2 ls of order eMcond(A), where eM is the machine precision and cond(A) = ||A || 2 ||A-1|| denotes the condition number of the matrix A.