Wyniki wyszukiwania - BazTech

1

Physical Implementation and Testing of Low-Power Adiabatic Flip-Flops with Energy-Recycling Pads

Jiang J., Hu J.

Przegląd Elektrotechniczny

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2012

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R. 88, nr 9b

192-195

EN

This paper presents adiabatic flip-flops based on CPAL (complementary pass-transistor adiabatic logic) circuits with energy-recycling output pad cells. The energy-recycling output pad cells for driving adiabatic chips include mainly bonding pads, ESD (electrostatic discharge) protection circuits, and two stage energy-recycling buffers. The adiabatic flip-flops and sequential circuits with energy-recycling output pad cells have been fabricated with Chartered 0.35um process. The adiabatic flip-flops have large energy savings over a wide range of frequencies.

PL

W artykule zaproponowano adiabatyczny przerzutnik bazujący na układach CPAL – complementary pass-transistor adiabatic logic). Zastosowano też blok wyjściowy z odzyskiwaniem energii.

2

Quasi-statyczny makromodel zatrzasku do optymalizacji metastabilności

Wieczorek P. Z.

Elektronika : konstrukcje, technologie, zastosowania

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2011

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Vol. 52, nr 9

178-181

PL

Prezentowana w niniejszej pracy koncepcja jest opisem behawioralnym układu przerzutnikowego (zatrzasku) na potrzeby modelowania i optymalizacji metastabilności. Układ przerzutnikowy w tej koncepcji złożony jest z intuicyjnych elementów elektrycznych takich jak wzmacniacze odwracające, pojemności inercyjne, rezystancje. Projektant układu ma więc wgląd w czysto elektryczne parametry układu a parametry te są analityczno-behawioralnie powiązane z parametrami projektowymi technologii CMOS.

EN

A novel concept of behavioral description of D-Latch is introduced. For the purpose of modeling and metastability optimization D-Latch circuit has been described as a Simulink macromodel. This novel macromodel based on simple and intuitive electrical elements and subcircuits joins technological CMOS parameters with easy to understand parameters. With use of presented macromodel the designer of a D-Latch circuit has insight into its electrical behavior during the metastable operation. Also a novel metastability measure has been introduced for the purpose of macromodel's optimization.

3

Design of Digital Circuits with Current-mode Gates

Guziński A., Pawłowski P., Czwyrow D., Kaniewski J., Maslennikow O., Maslennikowa N., Rataj D.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2000

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Vol. 48, nr 1

73-91

EN

The paper deals with the problem of digital circuit design based on the current-mode gates - novel digital elements operating with a constant, continuous power supply current. The purpose is the provision of a high level noise immunity of chips which contain both analog and digital circuits. The logical properties and several identities of the current-mode logic and some expressions for a conversion of the Boolean functions into the current-mode functions are represented. Based on these properties and expressions, the approaches of minimizing the current logic functions are derived. Moreover, a new concept of the low-voltage current-mode gates realization and the two new types of the current-mode gates are designed for the next reduction of the current mode digital circuit complexity. Based on these approaches and new types of the gates, the functional schemes of some current-mode combinatorial and sequential circuits are derived. The obtained circuits are characterized by lower hardware overheads (up to 35%) in comparison with similar hardware based on the classical voltage type gates.