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Firmware development for the fibre-optic seismometer based on FOG

Kamiński Marek, Tylman Wojciech, Jabłoński Grzegorz, Kotas Rafał, Amrozik Piotr, Sakowicz Bartosz, Jaroszewicz Leszek R.

Opto-Electronics Review

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2024

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Vol. 32, No. 2

art. no. e150179

EN

The main goal of the article is to present the concept of using a simulation environment when designing an advanced fibre-optic seismometer (FOS) using a field-programmable gate array (FPGA) computing system. The first part of the article presents the advanced requirements regarding the FOS principle of operation, as well as the measurement method using a closed-loop operation. The closed-loop control algorithm is developed using the high-level language C++ and then it is synthesised into an FPGA. The following part of the article describes the simulation environment developed to test the operation of the control algorithm. The environment includes a model of components of the measurement system, delays, and distortions in the signal processing path, and some of the measurement system surroundings. The article ends with a comparison of simulation data with measurements. The obtained results are consistent and prove correctness of the methodology adopted by the authors.

2

Employing FPGA DSP blocks for time-to-digital conversion

Kwiatkowski Paweł

Metrology and Measurement Systems

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2019

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Vol. 26, nr 4

631--643

EN

The paper presents a novel implementation of a time-to-digital converter (TDC) in field-programmable gate array (FPGA) devices. The design employs FPGA digital signal processing (DSP) blocks and gives more than two-fold improvement in mean resolution in comparison with the common conversion method (carry chain-based time coding line). Two TDCs are presented and tested depending on DSP configuration. The converters were implemented in a Kintex-7 FPGA device manufactured by Xilinx in 28 nm CMOS process. The tests performed show possibilities to obtain mean resolution of 4.2 ps but measurement precision is limited to at most 15 ps mainly due to high conversion nonlinearities. The presented solution saves FPGA programmable logic blocks and has an advantage of a wider operation range when compared with a carry chain-based time coding line.

3

A time-domain pulse amplitude and width discrimination method for photon counting

del Mar Correa M., Pérez F. R.

Metrology and Measurement Systems

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2018

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Vol. 25, nr 2

269--282

EN

This work shows a time-domain method for the discrimination and digitization of parameters of voltage pulses coming from optical detectors, taking into account the presence of electronic noise and afterpulsing. Our scheme is based on an FPGA-based time-to-digital converter as well as an adjustable-threshold comparator complemented with commercial elements. Here, the design, implementation and optimization of a multiphase TDC using delay lines shorter than a single clock period is also described. The performance of this signal processing system is discussed through the results from the statistical code density test, statistical distributions of measurements and information gathered from an optical detector. Unlike dual voltage threshold discriminators or constant-fraction discriminators, the proposed method uses amplitude and time information to define an adjustable discrimination window that enables the acquisition of spectra.

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FPGA implementation of logarithmic versions of Baum-Welch and Viterbi algorithms for reduced precision hidden Markov models

Pietras M., Klęsk P.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2017

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Vol. 65, nr 6

935--946

EN

This paper presents a programmable system-on-chip implementation to be used for acceleration of computations within hidden Markov models. The high level synthesis (HLS) and “divide-and-conquer” approaches are presented for parallelization of Baum-Welch and Viterbi algorithms. To avoid arithmetic underflows, all computations are performed within the logarithmic space. Additionally, in order to carry out computations efficiently – i.e. directly in an FPGA system or a processor cache – we postulate to reduce the floating-point representations of HMMs. We state and prove a lemma about the length of numerically unsafe sequences for such reduced precision models. Finally, special attention is devoted to the design of a multiple logarithm and exponent approximation unit (MLEAU). Using associative mapping, this unit allows for simultaneous conversions of multiple values and thereby compensates for computational efforts of logarithmic-space operations. Design evaluation reveals absolute stall delay occurring by multiple hardware conversions to logarithms and to exponents, and furthermore the experiments evaluation reveals HMMs computation boundaries related to their probabilities and floating-point representation. The performance differences at each stage of computation are summarized in performance comparison between hardware acceleration using MLEAU and typical software implementation on an ARM or Intel processor.

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Obserwator siły elektromotorycznej w silniku z magnesami trwałymi o strumieniu poprzecznym

Sobieraj T.

Przegląd Elektrotechniczny

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2016

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R. 92, nr 6

53--56

PL

W artykule przedstawiono metodę wyznaczania siły SEM w dwufazowym silniku z magnesami trwałymi o strumieniu poprzecznym podczas normalnej pracy układu napędowego. Algorytm wykorzystuje sygnały, które są mierzalne zewnętrznie, bez ingerencji w konstrukcję silnika (na przykład bez montowania dodatkowych czujników wewnątrz silnika). Jako platformę sprzętową zastosowano przekształtniki laboratoryjne (własne konstrukcje falowników). Nisko poziomowe bloki sterowania falowników (przełączanie kluczy, zabezpieczenia, pomiary, algorytmy sterowania) zostały oparte na module FPGA. Akwizycja sygnałów pomiarowych została zrealizowana na platformie dSpace. Praca zawiera wyniki symulacji i badań eksperymentalnych na odpowiednio zaprojektowanym stanowisku laboratoryjnym.

EN

In the paper author presents the method of back-EMF calculation in the permanent magnet transverse flux motor during normal operation of drive system. The algorithm uses externally measurable signals without interfering with the structure of the motor (e.g. without adding additional sensors inside the motor). Hardware platform is based on laboratory power inverters. Low-level control blocks (switching keys, protections, measurement, control algorithms) of the inverter uses an FPGA module. Measurements are implemented on dSpace platform. The work contains simulations and the results of experiments.