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The use of hierarchical structures for design of high-speed digital comparators on FPGA/SoC

Salauyou V.

Measurement Automation Monitoring

2016

Vol. 62, No. 6

196--198

This paper presents a design method of high-speed digital comparators on FPGA/SoC by means of hierarchical structures. A synthesis technique of hierarchical structures for comparators is offered. In this technique, the comparator best hierarchical structure is empirically found for a certain FPGA family. The proposed method allows reducing a delay for 256-bits comparators by 1.245 to 2.516 times as compared with a traditional approach, and for 512-bits comparators by 3.399 times. The method also allows reducing an area by 40.2% on occasion.