Wyniki wyszukiwania - BazTech

1

Synthesis of the configuration structure of digital receiver of NQR radiospectrometer

Hotra O., Samila A., Politansky L.

Przegląd Elektrotechniczny

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2018

|

R. 94, nr 7

58--61

EN

Analysis of methods for demodulation of free induction decay signal that are suitable for use in pulsed nuclear quadruple resonance radiospectrometers was performed. The structure and MATLAB Simulink model of the receive path of radiospectrometer was synthesized, in which the Software Defined Radio technology was chosen for the implementation of a quadrature detector with a filtration and quadrature reflection suppression system. The application of the principle of direct digitization of the signal made it possible to significantly reduce the length of the analog portion of the receiver, and, consequently, reduce the noise of the useful signal and the level of out-of-band higher order spectral components.

PL

Przeprowadzono analizę metod demodulacji sygnału zaniku indukcji swobodnej, które są odpowiednie do stosowania w impulsowych radiospektrometrach jądrowego rezonansu kwadrupolowego. Opracowano strukturę i model ścieżki odbiorczej radiospektromeru w środowisku MATLAB Simulink, w którym do realizacji kwadraturowego detektora z układem filtracji i tłumienia odbicia kwadraturowego wybrano oprogramowanie Software Defined Radio. Zastosowanie zasady bezpośredniej cyfryzacji sygnału pozwoliło znacznie zmniejszyć długość analogowej części odbiornika, a w konsekwencji zmniejszyć szum sygnału użytecznego oraz poziom pozapasmowych składowych widmowych wyższych rzędów.

2

An efficient hardware implementation of a combinations generator

Mazurkiewicz T.

Technical Sciences / University of Warmia and Mazury in Olsztyn

|

2017

|

nr 20(4)

405--413

EN

In this paper an area-efficient hardware implementation of a Bincombgen algorithm was presented. This algorithm generates all (n,k) combinations in the form of binary vectors. The generator was implemented using Verilog language and synthesized using Xilinx and Intel-Altera software. Some changes were applied to the original code, which allows our FPGA implementation to be more efficient than in the previously published papers. The usage of chip resources and maximum clock frequency for different values of n and k parameters are presented.

3

A High-Speed Fully Digital Phase-Synchronizer Implemented in a Field Programmable Gate Array Device

Frankowski R., Chaberski D., Kowalski M., Zieliński M.

Metrology and Measurement Systems

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2017

|

Vol. 24, nr 3

537--550

EN

Most systems used in quantum physics experiments require the efficient and simultaneous recording different multi-photon coincidence detection events. In such experiments, the single-photon gated counting systems can be applicable. The main sources of errors in these systems are both instability of the clock source and their imperfect synchronization with the excitation source. Below, we propose a solution for improvement of the metrological parameters of such measuring systems. Thus, we designed a novel integrated circuit dedicated to registration of signals from a photon number resolving detectors including a phase synchronizer module. This paper presents the architecture of a high-resolution (~60 ps) digital phase synchronizer module cooperating with a multi-channel coincidence counter. The main characteristic feature of the presented system is its ability to fast synchronization (requiring only one clock period) with the measuring process. Therefore, it is designed to work with various excitation sources of a very wide frequency range. Implementation of the phase synchronizer module in an FPGA device enabled to reduce the synchronization error value from 2.857 ns to 214.8 ps.

4

Pattern Classification of Fabric Defects Using a Probabilistic Neural Network and Its Hardware Implementation using the Field Programmable Gate Array System

Hasnat A., Ghosh A., Khatun A., Halder S.

Fibres & Textiles in Eastern Europe

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2017

|

Vol. 25, no. 1 (121)

42--48

EN

This study proposes a fabric defect classification system using a Probabilistic Neural Network (PNN) and its hardware implementation using a Field Programmable Gate Arrays (FPGA) based system. The PNN classifier achieves an accuracy of 98 ± 2% for the test data set, whereas the FPGA based hardware system of the PNN classifier realises about 94±2% testing accuracy. The FPGA system operates as fast as 50.777 MHz, corresponding to a clock period of 19.694 ns.

PL

W pracy zaprezentowano system klasyfikacji wad tkanin przy użyciu probabilistycznej sieci neuronowej (PNN) i przy zastosowaniu systemu Field Programmable Gate Array (FPGA). PNN pozwala na osiągnięcie dokładności 98 ± 2% dla zbioru danych testowych, podczas gdy system FPGA pozwala na osiągnięcie dokładności około 94 ± 2%. System FPGA pracuje przy częstotliwości 50,777 MHz, co odpowiada 19,694 ns.

5

A proposal of output speed multiplication technique for true random number generators based on ring oscillators

Matuszewski Ł., Kubczak P.

Measurement Automation Monitoring

|

2016

|

Vol. 62, No. 5

157--159

EN

Nowadays modern cryptographic systems require a tremendous amount of keys. Very fast random number generators (RNGs) are needed to produce those keys in the requested time, but what to do when a solution that is already in use reaches the maximum speed? The aim of the paper is to find the answer to this question. In addition, generated random numbers should not leave a cryptographic system, because according to the Kerckhoffs thesis, the security of the whole system should be based only on a key. The cryptographic system should be enclosed within a single chip. In order to check new ideas and prove them, there were used NIST 800-22 test suite and restarts mechanism. The basic concept of the generator built of ring oscillators is still the same; ring oscillators are combined by XOR gates tree. A single ring oscillator consists of inverter, latch and NAND. This kind of construction provides a tool to make synchronous start and stop of all oscillators and the restart mechanism technique is applied in this manner. The speed of generation was increased by using multiple parallel generator trees to generate instantly the whole n-bit word. The paper shows that reproduction of the base structure is not a simple method of increasing the speed of generator. Moreover, it is always important to carefully consider all new ideas, because even if the NIST statistical test suite is passed, there is a chance that the restart mechanism will show some correlations that can be used during attack on the system.

6

Rough Sets Based LEM2 Rules Generation Supported by FPGA

Kopczyński M., Grześ T., Stepaniuk J.

Fundamenta Informaticae

|

2016

|

Vol. 148, nr 1/2

107--122

EN

In this paper we propose a combination of capabilities of the FPGA based device and PC computer for rough sets based data processing resulting in generating decision rules. Presented architecture has been tested on the exemplary datasets. Obtained results confirm the significant acceleration of the computation time using hardware supporting rough set operations in comparison to software implementation.

7

Core for Large Datasets : Rough Sets on FPGA

Kopczyński M., Grześ T., Stepaniuk J.

Fundamenta Informaticae

|

2016

|

Vol. 147, nr 2/3

241--259

EN

This paper presents FPGA and softcore CPU based device for large datasets core calculation using rough set methods. Presented architectures have been tested on two real datasets by downloading and running presented solutions inside FPGA. Tested datasets had 1 000 to 10 000 000 objects. The same operations were performed in software implementation. Obtained results show the big acceleration in computation time using hardware supporting core generation in comparison to pure software implementation.

8

Research and Medical Transcranial Doppler System

Lewandowski M., Walczak M., Karwat P., Witek B., Karłowicz P.

Archives of Acoustics

|

2016

|

Vol. 41, No. 4

773--781

EN

A new ultrasound digital transcranial Doppler system (digiTDS) is introduced. The digiTDS enables diagnosis of intracranial vessels which are rather difficult to penetrate for standard systems. The device can display a color map of flow velocities (in time-depth domain) and a spectrogram of a Doppler signal obtained at particular depth. The system offers a multigate processing which allows to display a numer of spectrograms simultaneously and to reconstruct a flow velocity profile. The digital signal processing in digiTDS is partitioned between hardware and software parts. The hardware part (based on FPGA) executes a signal demodulation and reduces data stream. The software part (PC) performs the Doppler processing and display tasks. The hardware-software partitioning allowed to build a flexible Doppler platform at a relatively low cost. The digiTDS design fulfills all necessary medical standards being a new useful tool in the transcranial field as well as in heart velocimetry research.

9

DSP - FPGA Based Computing Platform for Control of Power Electronic Converters

Stando D., Chudzik P., Moradewicz A., Miśkiewicz R., Kaźmierkowski M. P.

Przegląd Elektrotechniczny

|

2015

|

R. 91, nr 12

1-6

EN

Modern power electronic converters (PECs) require electronic controllers with high capabilities of implementing new and more complex algorithms combined with internal high-speed communications interfaces. This paper presents the design and implementation of a research/industrial multiprocessor controller based on a floating-point digital signal processor (DSP) and field programmable gate array (FPGA) developed in the Laboratory of the Electrotechnical Institute, Warsaw, Poland. The DSP-FPGA platform configuration, and also current and voltage sensors used in PECs are discussed. Although, the developed digital platform can be used in a variety of PECs, this paper focuses on an example of a 15kVA DC-AC high frequency AC link converter for auxiliary power supply used in DC traction. The novelty of the presented converter topology lies in passive components elimination by offering an all silicon solution for AC–AC power conversion part. Selected experimental oscillograms illustrating operation of the developed converter with DSP-FPGA control are added.

PL

Nowoczesne przekształtniki energoelektroniczne wymagają wydajnych platform obliczeniowych pozwalających na implementacje złożonych algorytmów i szybkich wewnętrznych interfejsów komunikacyjnych. Artykuł ten prezentuje projekt i implementację płyty sterującej zawierającej procesor sygnałowy i układ programowalny, którą opracowano w Instytucie Elektrotechniki w Warszawie. Powstała platforma może być wykorzystywana do sterowania różnego rodzaju urządzeń energoelektronicznych, w tym artykule przedstawiono jej implementację w przetwornicy 15 kW AC-DC z wysokoczęstotliwościowym przekształtnikiem sprzęgającym AC do zasilania elektronarzędzi w trakcji elektrycznej. Innowacyjność prezentowanej przetwornicy polega na eliminacji elementów pasywnych poprzez zastosowanie bezpośredniego sprzęgu AC-AC. Przedstawione zostały również wybrane oscylogramy eksperymentalne prezentujące pracę powstałego urządzenia sterowanego przez platformę DSP-FPGA.

10

Pulse Sequence Shaper For Radiospectroscopy And Relaxation Methods In NQR

Bobalo Y., Hotra Z., Hotra O., Politans’kyy L., Samila A.

Metrology and Measurement Systems

|

2015

|

Vol. 22, nr 3

363--370

EN

A pulse sequence shaper for the pursuance of the research using a wide spectrum of radiospectroscopy and relaxation methods in NQR is proposed. The distinctive feature of this product is its implementation with the application of a multi-functional programmable frequency synthesizer suitable for high-speed amplitude and phase manipulations.

11

Digital random bit generators implemented in FPGAs offered by various manufacturers

Kubczak P., Matuszewski Ł., Jessa M., Łoza S.

Measurement Automation Monitoring

|

2015

|

Vol. 61, No. 7

293--295

EN

In cryptography, we require that a random sequence should have excellent statistical properties as well as non-deterministic character. Combining multiple independent sources of randomness using the modulo two operation, significantly improves the statistical properties of the generated sequences and also affects the accumulation of true randomness generated in the oscillator sources. This is a very promising method of producing random sequences. In this paper, we compare the implementations of the RO-based combined random generator in various FPGAs technologies offered by various manufactures (Xilinx, Altera, Lattice). In this research, we used a NIST 800-22 statistical test suite to assess the statistical properties. The results show that the method of producing strings with a combined generator is the method stable in terms of technology. The results are similar for implementation in all FPGA used in the experiment. So, the proposed generator can be implemented in various programmable structures together with other components of a cryptographic system.

12

A random number generator using ring oscillators and the Keccak as post-processing

Łoza S., Matuszewski Ł., Jessa M., Kubczak P.

Measurement Automation Monitoring

|

2015

|

Vol. 61, No. 7

290--292

EN

In cryptography, sequences of numbers with unpredictable elements are often required. Such sequences should pass all known statistical tests for random sequences. Because sequences produced in real circuits are biased, they do not pass many statistical tests, e.g., the distribution of numbers is not uniform. Such random number sequences should be subjected to a transformation called post-processing. In this paper, a true random number generator is considered. It uses ring oscillators and the Keccak hash function as post-processing. This paper presents only simulation conditions for this approach since the post-processing part was done using x86 architecture on a PC.

13

A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing

Łoza S., Matuszewski Ł., Jessa M.

International Journal of Electronics and Telecommunications

|

2015

|

Vol. 61, No. 2

199–204

EN

Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called postprocessing. In this paper the hash function SHA-256 as postprocessing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components – the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies.

14

FPGA realization of an improved alpha max plus beta min algorithm

Czyżak M., Smyk R.

Poznan University of Technology Academic Journals. Electrical Engineering

|

2014

|

No. 80

151--160

EN

The improved version of the alpha max plus beta min square-rooting algorithm and its realization in the Field Programmable Gate Array (FPGA) are presented. The algorithm computes the square root to calculate the approximate magnitude of a complex sample. It is especially useful for pipelined calculations in the DSP. The improved version allows to reduce the peak error from about 4% to 0.33%. This is attained by determination of the approximate ratio of arguments and adequate selection of algorithm coefficients. Four approximation regions are used and hence four sets of coefficients. Also a Xilinx FPGA implementation for 12-bit sign magnitude numbers is shown.

15

Wektorowy falownik napięciowy z pomiarem rzeczywistego napięcia wyjściowego

Nowak R., Chudzik P., Sobieraj T.

Napędy i Sterowanie

|

2014

|

R. 16, nr 4

70--73

PL

W artykule przedstawiono wektorowy falownik napięciowy zaprojektowany w Instytucie Automatyki Politechniki Łódzkiej, przeznaczony do badań laboratoryjnych silników synchronicznych z magnesami trwałymi. Główną cechą prezentowanego urządzenia jest możliwość elastycznej konfiguracji jednostki sterującej wyposażonej zarówno w mikrokontroler z rdzeniem ARM, jak również układ rekonfigurowalny FPGA. Dzięki takiemu rozwiązaniu uzyskano możliwość testowania algorytmów sterowania napędami przeznaczonymi zarówno do stosowania w układach sekwencyjnych (mikrokontrolery), jak również w układach programowalnych (FPGA). Zaletą urządzenia jest możliwość synergicznego podziału realizacji algorytmu pomiędzy te dwie obecnie najpowszechniej wykorzystywane architektury obliczeniowe. Opisano specjalnie zaprojektowany układ pomiarowy napięcia wyjściowego falownika. To autorskie rozwiązanie pozwala nie tylko zmniejszyć wymagania co do parametrów podzespołów analogowych użytych do budowy toru pomiarowego, ale również w znaczący sposób odciążyć jednostkę obliczeniową układu sterującego. W artykule omówiono przyjęte założenia projektowe oraz algorytmy działania urządzenia. Zamieszczono również wybrane przebiegi w charakterystycznych stanach pracy układu.

EN

The paper presents a power converter designed in the Institute of Automatic Control Lodz University of Technology intended for laboratory tests PMSM motors. The main feature of the presented device is the ability to flexibly configure the control unit that contains both the ARM microcontroller core and the reconfigurable FPGA system. This solution achieved the possibility of testing the drive control algorithms intended for use in both the sequential circuits (MCUs), as well as programmable circuits (FPGA). Advantage is the possibility of synergistic implementation of the algorithm, the division between the two currently most widely used computing architectures. Describes the specially designed true output voltage measurement system. This proprietary solution allows not only to reduce the demands on the performance of analog components used in the construction of the measuring circuit, but also significantly relieve the unit of account by the control system. The paper contains a discussion of the assumptions and algorithms design performance. It also provides selected waveforms in typical operating conditions of the system.

16

Development of an embedded FPGA-based data acquisition system dedicated to zero power reactor noise experiments

Arkani M., Khalafi H., Vosoughi N.

Metrology and Measurement Systems

|

2014

|

Vol. 21, nr 3

433--446

EN

An embedded time interval data acquisition system (DAS) is developed for zero power reactor (ZPR) noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA). The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit x 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure design. As the architecture can work on a typical FPGA, this is a low cost experimental tool and needs little time to be established. In addition, revisions are easily possible through its reprogramming capability. The performance of the system is checked and verified experimentally.

17

Comparison of three different 2-D space vector PWM algorithms and their FPGA implementations

Bishuang F., Guanzheng T., Shaosheng F.

Journal of Power Technologies

|

2014

|

Vol. 94, nr 3

176--189

EN

To improve the flexibility of the multilevel space vector pulse width modulation (SVPWM), various algorithms have been developed. A theoretical comparison is made for three 2-D SVPWM algorithms: they are g-h frame, α' - β' frame and multilevel SVPWM based on two-level (α* - β* frame). The aim is to provide a guideline for the selection of the most appropriate SVPWM technique for digital implementation. Among them, the α' - β' frame offers the best flexibility with the least calculation and is well suited for digital implementation. The α* - β* frame is the most intuitionistic but has the largest calculation. New general methods of the g-h frame and α' - β' frame for any level SVPWM are also provided, which needs only the angle θ and the modulation depth m to generate and arrange the final vector sequence. All three methods are implemented in a field programmable gate array (FPGA) with very high speed integrated circuit hardware description language (VHDL) and compared in terms of implementation complexity and logic resources required. Simulation results show the absolute advantages of α' - β' frame in briefness and resources use. Finally, an experimental test result is presented with a three-level neutral-point-clamped (NPC) inverter.

18

A digital true random number generator implemented in different Xilinx FPGAs

Matuszewski Ł., Jessa M.

Pomiary Automatyka Kontrola

|

2013

|

R. 59, nr 8

742--744

EN

In cryptography we often require sequences of numbers with unpredictable elements. Such sequences cannot be produced by purely deterministic systems. A novel method for producing true randomness and increasing the randomness of a combined TRNG using ring oscillators is described. In this paper we show that the proposed method provides similar results for generators implemented using different technologies offered by Xilinx. Thus, the proposed generator can be implemented in different FPGAs with other elements of a cryptographic system.

PL

W kryptografii często wymaga się ciągów liczb złożonych z nieprzewidywalnych elementów. Takie sekwencje nie mogą być wytwarzane w systemach czysto deterministycznych. Inżynierowie muszą opracować źródła losowości, których właściwości muszą być ocenione i potwierdzone przez niezależne badania, przynajmniej doświadczalnie. W artykule pokazano, że proponowana metoda wytwarzania losowości jest stabilna pod względem technologicznym. Uzyskano bardzo zbliżone rezultaty dla generatorów losowych zrealizowanych w strukturach FPGA (Field Programmable Gate Array) wykonanych w różnych technologiach jakie oferuje firma Xilinx. W żadnym przypadku nie korzystano z manualnego rozmieszczania elementów w matrycy FPGA, aby uzyskać lepsze rezultaty. Położenie poszczególnych składników zależało tylko od oprogramowania dostarczanego przez producenta. Zatem proponowany generator może być implementowany w różnych układach FPGA razem z innymi elementami systemu kryptograficznego.

19

Wektorowy falownik napięciowy z pomiarem rzeczywistego napięcia wyjściowego

Nowak R., Chudzik P., Sobieraj T.

Maszyny Elektryczne : zeszyty problemowe

|

2013

|

Nr 2(99)

179--183

PL

W artykule przedstawiono wektorowy falownik napięciowy zaprojektowany w Instytucie Automatyki Politechniki Łódzkiej przeznaczony do badań laboratoryjnych silników synchronicznych z magnesami trwałymi. Główną cechą prezentowanego urządzenia jest możliwość elastycznej konfiguracji jednostki sterującej wyposażonej zarówno w mikrokontroler z rdzeniem ARM, jak również układ rekonfigurowalny FPGA. Dzięki takiemu rozwiązaniu uzyskano możliwość testowania algorytmów sterowania implementowanych zarówno w układach sekwencyjnych (mikrokontrolery), jak również w układach programowalnych (FPGA). Zaletą urządzenia jest możliwość synergicznego podziału realizacji algorytmu pomiędzy te dwie obecnie najpowszechniej wykorzystywane architektury obliczeniowe. Opisano specjalnie zaprojektowany układ pomiarowy napięcia wyjściowego falownika. To autorskie rozwiązanie pozwala nie tylko zmniejszyć wymagania co do parametrów podzespołów analogowych użytych do budowy toru pomiarowego, ale również w znaczący sposób odciążyć jednostkę obliczeniową układu sterującego. W artykule omówiono przyjęte założenia projektowe oraz algorytmy działania urządzenia. Zamieszczono również wybrane przebiegi w charakterystycznych stanach pracy układu.

EN

The paper presents a power converter designed in the Institute of Automatic Control Lodz University of Technology intended for laboratory tests PMSM motors. The main feature of the presented device is the ability to flexibly configure the control unit that contains both the ARM microcontroller core and the reconfigurable FPGA system. Thanks to this solution one has possibility of testing the drive control algorithms intended for use in both the sequential circuits (MCUs), as well as programmable circuits (FPGA). Advantage is the possibility of synergistic implementation of the algorithm, the division between the two currently most widely used computing architectures. Describes the specially designed true output voltage measurement system. This proprietary solution allows not only to reduce the demands on the performance of analog components used in the construction of the measuring circuit, but also significantly relieve the unit of account by the control system. The paper contains a discussion of the assumptions and algorithms design performance. It also provides selected waveforms in typical operating conditions of the system.

20

FPGA implementations of low precision floating point multiply-accumulate

Amaricai A., Boncalo O., Sicoe O

International Journal of Microelectronics and Computer Science

|

2013

|

Vol. 4, nr 4

159--163

EN

Floating point (FP) multiply-accumulate (MAC) represents one of the most important operations in a wide range of applications, such as DSP, multimedia or graphic processing. This paper presents a FP MAC half precision (16-bit) FPGA implementation. The main contribution of this work is represented by the utilization of modern FPGA DSP block for performing both mantissa multiplication and mantissa accumulation. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on one of the multiplicand, and, a left shift for the other. This results in efficient DSP usage; thus both cost savings and higher performance (high working frequencies and low latencies) are targeted for MAC operations.