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Ekstrakcja równoległości w programach ANSI C dla systemów osadzonych

Bielecki W., Siedlecki K., Kraska K.

Pomiary Automatyka Kontrola

2010

R. 56, nr 7

697-700

W artykule zaprezentowano nowe podejście do ekstrakcji równole-głości w programach ANSI C dla architektur wieloprocesorowych polega-jące na wyznaczaniu niezależnych fragmentów obliczeń w pętlach programowych dowolnie zagnieżdżonych. Przedstawione podejście pozwala na ekstrakcję równoległości dla szerszego spektrum pętli programowych w porównaniu z transformacjami afinicznymi, uznawanymi dotychczas za najbardziej efektywne. Przedstawiono analizę zastosowania proponowanego podejścia dla wybranych źródeł języka ANSI C. Omówiono wyniki badań eksperymentalnych oraz wskazano kierunki dalszych prac.

The application of embedded computer systems extends from small consumer products to complex industrial solutions. Performance critical solutions require application of more efficient controllers using parallel architectures such as VLIW or multiprocessor (multi cores) architectures. The interest in using the parallelism in embedded systems puts up new challenges for science and engineering and requires new methods and tools. The paper presents a new approach to the extraction of parallelism in ANSI C programs for multiprocessor architectures, consisting of synchronization free threads of computations (slices). The presented approach allows the extraction of parallelism on a wider range of program loops than that extracted by the affine transformation framework identified as the most efficient. Scientific results achieved are implemented as an academic source to source parallelizing compiler. The analysis of applying the approach to selected ANSI C sources is presented. Experimental results are depicted and discussed. Conclusions and future research are discussed.

Wbudowany system komputerowy jako sterownik płyt kontrolno-pomiarowych do sterowania LLRF w akceleratorze

Zabołotny W. M., Roszkowski P., Husejko M., Romaniuk R. S., Poźniak K. T., Kierzkowski K.

Elektronika : konstrukcje, technologie, zastosowania

2005

Vol. 46, nr 7

61-64

Artykul zawiera ogolne rozwazania na temat przydatnosci wbudowanych systemow komputerowych do realizacji systemow sterowania w ptytach kontrolno-pomiarowych dla eksperymentow fizyki wysokiej energii. Oprocz tego przedstawiono opis prototypowego wbudowanego systemu komputerowego, umozliwiajacego sterowanie ptytami LLRF projektu TESLA. Stowa kluczowe:

The paper presents general considerations regarding application of embedded computer systems as controllers for control & measurement boards in high energy physics experiments. The paper describes also an example implementation of the embedded control system used for LLRF boards in TESLA experiment.

Formal Refinement Checking in a System-level Design Methodology

Talpin J.-P., Le Guernic P., Shukla S.K., Doucet F., Gupta R.

Fundamenta Informaticae

2004

Vol. 62, nr 2

243--273

Rising complexity, increasing performance requirements, and shortening time-to-market demands necessitate newer design paradigms for embedded system design. Such newer design methodologies require raising the level of abstraction for design entry, reuse of intellectual property blocks as virtual components, refinement based design, and formal verification to prove correctness of refinement steps. The problem of combining various components from different designers and companies, designed at different levels of abstraction, and embodying heterogeneous models of computation is a difficult challenge for the designer community today. Moreover, one of the gating factors for widespread adoption of the system-level design paradigm is the lack of formal models, method and tools to support refinement. In the absence of provably correct and adequate behavioral synthesis techniques, the refinement of a system-level description towards its implementation is primarily a manual process. Furthermore, proving that the implementation preserves the properties of the higher system-level design-abstraction is an outstanding problem. In this paper, we address these issues and define a formal refinement-checking methodology for system-level design. Our methodology is based on a polychronous model of computation of the multi-clocked synchronous formalism Signal. This formalism is implemented in the Polychrony workbench. We demonstrate the effectiveness of our approach by the experimental case study of a SpecC modeling example. First, we define a technique to systematically model SpecC programs in the Signal formalism. Second, we define a methodology to compare system-level models of SpecC programs and to validate behavioral equivalence relations between these models at different levels of abstraction. Although we use SpecC modeling examples to illustrate our technique, our methodology is generic and language-independent and the model that supports it conceptually minimal by offering a scalable notion and a flexible degree of abstraction.