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Design of high-performance PFD-CP for 403MHz CMOS fractional-N frequency synthesizer

Saleh S., Hamdy G., Elsemary H., Zaki A.

International Journal of Microelectronics and Computer Science

2017

Vol. 8, nr 3

97--100

This brief discusses the challenges and employs a novel charge-pump and a PFD/CP linearization technique to improve the performance of a 403MHz fractional-N PLL. Techniques are proposed to improve the linearity of the PLL by forcing the PFD/CP to operate in a linear part of its transfer characteristics, while the charge-pump minimizes the current mismatch between the up and down currents by using feedback. The circuit is designed in 0.13jim CMOS process and consumes a total power of 2.6mW. The simulation results show that the synthesizer has a phase noise of-128dBc/Hz at 1MHz offset.