Wyniki wyszukiwania - BazTech

1

Towards the perfect decimator

Hejn K.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

26-33

EN

In this paper a two-phase recursive all-pass network for sampling-rate reduction is presented in which efficiency is achieved by simple binary scaling coefficients and by performing all necessary processing at the half sampling rate. This . network is formed as a sum of two parallel all-pass subf liters with phase shifts selected to add constructively in the passband and destructively in the stop band. The proposed structures offer very desirable properties in comparison to most published sigma-delta implementations which use a blend of simple comb filtering and decimated FIR filters for the post-modulator decimation filtering.

2

Fixedpoint arihmetic effects in all-pass filters of oversampling sigma-delta (analog to digital) converters

Dąbrowski P., Baraniecki R., Hejn K., Rosiński A.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

113-118

EN

Oscillations arising from two's complement arithmetic rounding applied in all-pass filters are described. The all-pass filters in two-path phase shifter structure build a digital filter of oversampling sigma-delta converter - decimator. The paper also shows that during a top-down design process of the all-pass filters such oscillations can easily be suppressed.

3

An insight a digital sensor for delta-sigma modulator investigation

Hejn K., Krukowski A.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

58-61

EN

Even an ideal delta-sigma modulator exhibits certain nonlinear behaviour. So its comprehensive analytical description has been both an absorbing and confusing task. Hence simulation and measurement are the key factor for a successful evaluation of the delta-sigma structure. This work is about high-quality decimation filters (digital sensors) for delta-sigma modulator investigations. They are based on a two-phase (two-branch) parallel structure using recursive allpasses which are particularly suitable for decimation by a factor of two. Moreover the repeated use of a basic decimation stage (BDS) makes this structure highly modular and well fittted for silicon implementation. An important BDS with only three coefficients (1/8, 9/16 and -1/16) has been presented in detail. Applied in the five stage decimaior and compatible with CMOS technology, it achieves a 20-bit processing accuracy for the passband of 20 kHz -without the design complexity and cost penalties incurred in alternative approaches. The paper includes some design results with performance evaluation under fixed point arithmetic. The in-situ developed software tools are also described.

4

An HDL-A/VHDL model of an oversampling sigma-delta analog to digital converter

Baraniecki R., Dąbrowski P., Hejn K.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

120-127

EN

The paper presents a mixed HDL-A/VHDL model of an oversampling sigma-delta analog-to-digital converter created on the behavioural hierarchy level. The model of the analog part is coded in HDL-A and includes only necessary parameters that enable to determine the potential resolution of the converter. The model of the digital part is described in the synthesizable subset of VHDL and parameterized according to the word length and the type of arithmetic applied. Simulation results enclosed prove the efficiency of the design approach presented.

5

A VHDL model of an oversampling sigma-delta analogto digital converter

Dąbrowski P., Baraniecki R., Hejn K., Rosiński A.

Prace Przemysłowego Instytutu Elektroniki

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1998

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nr 132

87-92

EN

The IEEE Std. 1076 of VHDL has been primarily devoted to digital circuits' design. However, it can also be applied to certain mixed-signal circuits. An oversampling sigma-delta analog to digital converter has been chosen as a suitable example for behavioral modeling and simulation. The efficiency of the approach is analyzed in the SIGNAL PROCESSING WORKSYSTEM and VANTAGE Spreadsheet environments.