Wyniki wyszukiwania - BazTech

1

Analog Circuits Sizing Using the Fixed Point Iteration Algorithm with Transistor Compact Models

Javid F., Iskander R., Durbin F., Louerat M.-M.

International Journal of Microelectronics and Computer Science

|

2012

|

Vol. 3, nr 1

7-14

EN

This paper presents an algorithm, based on the fixed point iteration, to solve for sizes and biases using transistor compact models such as BSIM3v3, BSIM4, PSP and EKV. The proposed algorithm simplifies the implementation of sizing and biasing operators. Sizing and biasing operators were originally proposed in the hierarchical sizing and biasing methodology [1]. They allow to compute transistors sizes and biases based on transistor compact models, while respecting the designer's hypotheses. Computed sizes and biases are accurate, and guarantee the correct electrical behavior as expected by the designer. Sizing and biasing operators interface with a Spice-like simulator, allowing possible use of all available compact models for circuit sizing and biasing over different technologies. A bipartite graph , that contains sizing and biasing operators, is associated to the design view of a circuit, it is the design procedure for the given circuit. To illustrate the effectiveness of the proposed fixed point algorithm, a folded cascode OTA is efficiently sized with a 130nm process, then migrated to a 65nm technology. Both sizing and migration are performed in a few milliseconds.

2

Methodology for Implementing Scalable Run-Time Reconfigurable Devices

Kotynia Ł., Amrozik P., Napieralski A.

International Journal of Electronics and Telecommunications

|

2011

|

Vol. 57, No. 2

177-183

EN

The aim of this paper is to present the implementation methodology for an ASIC constituting the fine-grained array of dynamically reconfigurable processing elements. This methodology was developed during the work on a device which can operate as a typical Field Programmable Gate Array (FPGA) with some bio-inspired features or as a multi-core Single Instruction Multiple Data (SIMD) processor. Such high diversity of possible operating modes makes the design implementation extremely demanding. As a consequence, the comprehensive study and analysis of the different possible implementation techniques in this case allowed us to formulate a consistent and complete methodology that can be applied to other systems of similar structure.

3

Integrating USB functionality into system-on-chip : elements of the technical solution

Kaczmarczyk D., Sakowski W.

Elektronika : konstrukcje, technologie, zastosowania

|

2006

|

Vol. 47, nr 11

55-58

EN

The paper presents briefly an architecture of USB OTG controller IP core in the context of experiences gained during the earlier design work on USB device controllers. Universal Serial Bus is an industry standard conceived in the late 90's of 20th century to replace serial links used as a standard interface between personal computers and peripherals (USB OTG is an extension of USB standard). The presentation of the USB OTG controller IP core is followed with a discussion of numerous aspects of reusability that go beyond creating a synthesizable description of the controller at register transfer level.

PL

Artykuł zwięźle przedstawia architekturę kontrolera USB OTG w kontekście wcześniejszych doświadczeń projektowych nad kontrolerami urządzeń USB. Uniwersalna Magistrala Szeregowa jest standardem przemysłowym zdefiniowanym w latach dziewięćdziesiątych ubiegłego wieku w celu zastąpienia łączy szeregowych stanowiących standardowy interfejs pomiędzy komputerami personalnymi i urządzeniami peryferyjnymi. (USB OTG jest rozszerzeniem standardu USB). Prezentacja kontrolera uzupełniona jest dyskusją aspektów wspomagających wykorzystanie elektronicznych komponentów wirtualnych.