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Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments

Kapoor H.K., Josephs M.B., Furey D.P.

Fundamenta Informaticae

2006

Vol. 70, nr 1,2

21-48

A delay-insensitive module communicates with its environment through wires of unbounded delay. To avoid transmission interference, the absorption of a signal transition must be acknowledged before another one is propagated along the same wire. The environment may guarantee, however, to interact with the module in an even more restrictive way. It is worthwhile taking this into account when synthesising the module because it may allow for a cheaper, faster implementation. The concept of restriction has been built into our translation tool, di2pn (to help in synthesis), and our analysis tool, diana (to perform equivalence and refinement checking). Formally, DI-Algebra is equipped with a new operator that weakens the specification of a module by taking its environment into account. This operator is a useful instance of divergence extension, a concept introduced by Mallon. Divergence extension in general, and restriction and alternation in particular, can be represented with the parallel composition operator and so are amenable to algebraic reasoning.

Embedding Universal Delay-Insensitive Circuits in Asynchronous Cellular Spaces

Lee J., Adachi S., Peper F., Morita K.

Fundamenta Informaticae

2003

Vol. 58, nr 3,4

295--320

Asynchronous Cellular Automata (ACA) are cellular automata which allow cells to be updated at times that are random and independent of each other. Due to their unpredictable behavior, ACA are usually dealt with by simulating a timing mechanism that forces all cells into synchronicity. Though this allows the use of well-established synchronous methods to conduct computations, it comes at the price of an increased number of cell states. This paper presents a more effective approach based on a 5-state ACA with von Neumann neighborhood that uses rotation- and reflection-symmetric transition rules to describe the interactions between cells. We achieve efficient computation on this model by embedding so-called Delay-Insensitive circuits in it, a type of asynchronous circuits in which signals may be subject to arbitrary delays, without this being an obstacle to correct operation. Our constructions not only imply the computational universality of the proposed cellular automaton, but also allow the efficient use of its massive parallelism, in the sense that the circuits operate in parallel and there are no signals running around indefinitely in the circuits in the absence of input.