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1

Improving characteristics of LUT-based Mealy FSMs

Barkalov Alexander, Titarenko Larysa, Mielcarek Kamil

International Journal of Applied Mathematics and Computer Science

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2020

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Vol. 30, no. 4

745--759

EN

Practically, any digital system includes sequential blocks represented using a model of finite state machine (FSM). It is very important to improve such FSM characteristics as the number of logic elements used, operating frequency and consumed energy. The paper proposes a novel technology-dependent design method targeting a decrease in the number of look-up table (LUT) elements and their levels in logic circuits of FPGA-based Mealy FSMs. It produces FSM circuits having three levels of logic blocks. Also, it produces circuits with regular systems of interconnections between the levels of logic. The method is based on dividing the set of internal states into two subsets. Each subset corresponds to a unique part of an FSM circuit. Only a single LUT is required for implementing each function generated by the first part of the circuit. The second part is represented by a multi-level circuit. The proposed method belongs to the group of two-fold state assignment methods. Each internal state is encoded as an element of the set of states and as an element of some of its subsets. A binary state assignment is used for states corresponding to the first part of the FSM circuit. The one-hot assignment is used for states corresponding to the second part. An example of FSM synthesis with the proposed method is shown. The experiments with standard benchmarks are conducted to analyze the efficiency of the proposed method. The results of experiments show that the proposed approach leads to diminishing the number of LUTs in the circuits of rather complex Mealy FSMs having more than 15 internal states. The positive property of this method is a reduction in energy consumption (without any overhead cost) and an increase in operating frequency compared with other investigated methods.

2

Quality testing model for unit prototype technological devices

Dobrodziej J., Mazurkiewicz A., Zbrowski A.

Scientific Problems of Machines Operation and Maintenance

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2011

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Vol. 46, nr 1

29-44

EN

The article presents the model of testing individually manufactured unique prototype technical devices. Furthermore, problems occurring in such prototype testing are identified, and, on the basis, the assumptions of the model for quality tests of prototype technical solutions are made. Essential components of the model, including structural and process decomposition procedures, are discussed. Moreover, potential applications of the model are analysed and indicated. Results of the model verification are presented using the example of selected, technologically advanced prototype devices.

PL

W artykule przedstawiono model badania prototypowych urządzeń technicznych wytwarzanych jednostkowo. Zidentyfikowano praktyczne problemy występujące w badaniach takich prototypów. Na tej podstawie sformułowano założenia do budowy modelu badań jakości rozwiązań prototypowych. Zaprezentowano kluczowe komponenty modelu, w tym procedury dekompozycji strukturalnej i procesowej. Przeanalizowano możliwości zastosowań modelu. Weryfikację modelu przedstawiono na wybranych, zaawansowanych technicznie prototypowych jednostkowych urządzeniach technicznych.

3

Wielokrotne kodowanie stanów i mikroinstrukcji automatów implementowanych w strukturach FPGA

Bukowiec A., Barkalov A.

Elektronika : konstrukcje, technologie, zastosowania

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2009

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Vol. 50, nr 10

35-37

PL

W artykule przedstawiono metody syntezy skończonych automatów stanów do struktur FPGA z zastosowaniem dekompozycji strukturalnej i wielokrotnego kodowania. Stany automatu oraz mikroinstrukcje są dzielone na podzbiory i kodowane oddzielnie w każdym z nich. Następnie są one dekodowane w układzie drugiego poziomu. Prowadzi to do realizacji układu logicznego automatu w strukturze dwupoziomowej. Rozwiązanie takie zapewnia zbalansowane wykorzystanie dostępnych zasobów sprzętowych, takich jak tablice LUT i osadzone bloki pamięci, w nowoczesnych układach FPGA.

EN

There are presented methods of synthesis of automata into FPGAs with architectural decomposition and multiple encoding in this article. States and microinstructions are divided into subsets and they are encoded separately in each subset. Next, they are decoded in the second level circuit. It leads to realization of logic circuit of automaton in double-level structure. It leads to balanced utilization of available hardware resources, like LUTs and embedded memory blocks, of modern FPGA devices.