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Graphene-based Current Mode Logic Circuits : a Simulation Study for an Emerging Technology

Abdollahi Hassan, Hooshmand Reza, Owlia Hadi

International Journal of Electronics and Telecommunications

2019

Vol. 65, No. 3

381--388

In this paper, the usage of graphene transistors is introduced to be a suitable solution for extending low power designs. Static and current mode logic (CML) styles on both nanoscale graphene and silicon FINFET technologies are compared. Results show that power in CML styles approximately are independent of frequency and the graphene-based CML (G-CML) designs are more power-efficient as the frequency and complexity increase. Compared to silicon-based CML (Si-CML) standard cells, there is 94% reduction in power consumption for G-CML counterparts. Furthermore, a G-CML 4-bit adder respectively offers 8.9 and 1.7 times less power and delay than the Si-CML adder.

Design of Digital Circuits with Current-mode Gates

Guziński A., Pawłowski P., Czwyrow D., Kaniewski J., Maslennikow O., Maslennikowa N., Rataj D.

Bulletin of the Polish Academy of Sciences. Technical Sciences

2000

Vol. 48, nr 1

73-91

The paper deals with the problem of digital circuit design based on the current-mode gates - novel digital elements operating with a constant, continuous power supply current. The purpose is the provision of a high level noise immunity of chips which contain both analog and digital circuits. The logical properties and several identities of the current-mode logic and some expressions for a conversion of the Boolean functions into the current-mode functions are represented. Based on these properties and expressions, the approaches of minimizing the current logic functions are derived. Moreover, a new concept of the low-voltage current-mode gates realization and the two new types of the current-mode gates are designed for the next reduction of the current mode digital circuit complexity. Based on these approaches and new types of the gates, the functional schemes of some current-mode combinatorial and sequential circuits are derived. The obtained circuits are characterized by lower hardware overheads (up to 35%) in comparison with similar hardware based on the classical voltage type gates.