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Why Is White Noise Not Enough? Using Radio Front-End Models While Designing 6G PHY

Kryszkiewicz Pawel, Sroka Pawel, Hoﬀmann Marcin, Wachowiak Marcin

Journal of Telecommunications and Information Technology

2023

nr 2

41--45

Each subsequent generation of wireless standards imposes stricter spectral and energy eﬃciency demands. So far, layered wireless transceiver architectures have been used, allowing for instance to separate channel decoding algorithms from the front-end design. Such an approach may need to be reconsidered in the upcoming 6G era. Especially hardware-originated distortions have to be taken into account while designing other layer algorithms, as high throughput and energy eﬃciency requirements will push these devices to their limits, revealing their non-linear characteristics. In such a context, this paper will shed some light on the new degrees of freedom enjoyed while cross-layer designing as well as controlling multicarrier and multiantenna transceivers in 6G systems.

High-Level Design Methodology for Ultra-Fast Software Defined Radio Prototyping on Heterogeneous Platform

Moy Ch., Raulet M.

Advances in Electronics and Telecommunications

2010

Vol. 1, no. 1

67--85

The design of Software Defined Radio (SDR) equipments (terminals, base stations, etc.) is still very challenging. We propose here a design methodology for ultra-fast prototyping on heterogeneous platforms made of GPPs (General Purpose Processors), DSPs (Digital Signal Processors) and FPGAs (Field Programmable Gate Array). Lying on a component-based approach, the methodology mainly aims at automating as much as possible the design from an algorithmic validation to a multi-processing heterogeneous implementation. The proposed methodology is based on the SynDEx CAD design approach, which was originally dedicated to multi-GPPs networks. We show how this was changed so that it is made appropriate with an embedded context of DSP. The implication of FPGAs is then addressed and integrated in the design approach with very little restrictions. Apart from a manual HW/SW partitioning, all other operations may be kept automatic in a heterogeneous processing context. The targeted granularity of the components, which are to be assembled in the design flow, is roughly the same size asthat of a FFT, a filter or a Viterbi decoder for instance. The reuse of third party or predeveloped IPs is a basis for this design approach. Thanks to the proposed design methodology it is possible to port “ultra” fast a radio application over several platforms. In addition, the proposed design methodology is not restricted to SDR equipment design, and can be useful for any real-time embedded heterogeneous design in a prototyping context.