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1

Xilinx Virtex-4 jako platforma rozwojowa jednostek centralnych PLC

Chmiel M., Mocha J., Hrynkiewicz E.

Pomiary Automatyka Kontrola

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2011

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R. 57, nr 1

55-57

PL

Artykuł prezentuje koncepcję platformy sprzętowo-programowej umożliwiającej testowanie różnych rozwiązań konstrukcyjnych jednostek centralnych sterowników programowalnych. Platforma do testowania jednostek bazuje na układzie FPGA Virtex-4 oraz opracowanym dedykowanym oprogramowaniu narzędziowym, umożliwiającym testowanie oraz badania właściwości opracowywanych jednostek. Przedstawiono wybrane dwuprocesorowe bitowo-bajtowe jednostki spotykane w literaturze, zorientowane na maksymalnie efektywne wykorzystanie obydwu procesorów. Szczególną uwagę zwrócono na szybkość wykonywania programu sterowania oraz funkcjonalność jednostki.

EN

To develop fast central processing units (CPUs) of programmable logic controllers (PLC) one can employ the architecture with two processors: a bit and a byte processor. The bit processor shall be responsible for processing the bit variables, while the byte processor shall be meant to deal with the byte (word) variables [1, 2, 3, 4, 5, 6]. In case of the double-processor architecture it is extremely important to synchronize operation of data exchange between the processors. The literature references report various synchronization methods [9, 10, 11, 12] that are described in Section 3. Sections 4 and 5 outline the combined hardware and software platform intended to enable testing and comparison between various architectures of CPUs. The presented solution employs a programmable FPGA module from the Virtex-4 family [7, 8], that are described in Section 2. The newly developed software enables compilation of application programs dedicated for the presented architecture. To develop programs for the presented solution the authors used the assembler-type programming language very similar to STL language that is normally applicable to STL controllers from Siemens [13, 14]. The software developed for PC computers make it possible to define new instructions for processors both on hardware and software levels (Fig. 1). The presented solution takes advantage of components that are typical for FPGA modules, such as BockRAM memory units (Fig. 2). The presented platforms enable further research and development efforts intended to design fast CPUs for programmable logic controllers.

2

Concurrent operation of processors in the bit-byte CPU of a PLC

Chmiel M., Hrynkiewicz E.

Control and Cybernetics

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2010

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Vol. 39, no 2

559-579

EN

The paper presents some selected hardware solutions for the PLC dual processor bit-byte CPUs, which are oriented at optimised data exchange between the CPU processors. The optimisation aims at maximum utilisation of capabilities of the two-processor architecture of the CPU. The key point is preserving high speed of instruction processing by the bit-processor, and high functionality of the byte-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimise the situations, when one processor has to wait for the other.

3

On reducing PLC response time

Chmiel M.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2008

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Vol. 56, nr 3

229-238

EN

The dual core bit-byte CPU must be equipped with properly designed circuits, providing interface between the two processor units, and making it possible to exploit all its advantages like versatility of the byte unit and speed of the bit unit. First of all, the interface circuits should be designed in such a way, that they don't disturb maximally parallel operation of the units, and that the CPU as a whole works in the same manner as in a standard PLC. The paper presents hardware solutions supporting effective operation of PLC CPU-so Possibilities of solving problems concerning data exchange between a CPU and peripheral circuits were presented, with a special stress on timers and counters, and also on data exchange between the bit unit and the byte unit. The objective of the proposed solutions is to decrease the time necessary for a CPU to access its peripheries.