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1

Realization of logic integrated circuits in VeSTIC process - design, fabrication, and characterization

Domański Krzysztof, Głuszko Grzegorz, Sierakowski Andrzej, Tomaszewski Daniel, Szmigiel Dariusz

International Journal of Microelectronics and Computer Science

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2018

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Vol. 9, nr 3

123--132

EN

A design and manufacturing of test structures for characterization of logic integrated circuits in a VeSTIC process developed in ITE, are described. Two variants of the VeSTIC processs have been described. A role and sources of the process variability have been discussed. The VeSFET I-V characteristics, the logic cell static characteristics, and waveforms of the 53-stage ring oscillator are presented. Basic parameters of the VeSFETs have been determined. The role of the process variability and of the parasitic elements introduced by the conservative circuit design, e.g. wide conductive lines connecting the devices in the circuits, have been discussed. Based on the inverter layout and on the process specification, the parasitic elements of the inverter equivalent circuit have been extracted. The inverter propagation times, the ring oscillator frequency, and their dependence on the supply bias have been determined.

2

Area equivalent WKB Compact modeling approach for tunneling probability in Hetero-Junction TFETs including ambipolar behaviour

Horst Fabian, Farokhnejad Atieh, Darbandy Ghader, Iñíguez Benjamín, Kloes Alexander

International Journal of Microelectronics and Computer Science

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2018

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Vol. 9, nr 2

47--59

EN

This paper introduces an innovative modeling approach for calculating the band-to-band (B2B) tunneling probability in tunnel-field effect transistors (TFETs). The field of application is the usage in TFET compact models. Looking at a tunneling process in TFETs, carriers try to tunnel through an energy barrier which is defined by the device band diagram. The tunneling energy barrier is approximated by an approach which assumes an area equivalent (AE) triangular shaped energy profile. The simplified energy triangle is suitable to be used in the Wentzel-Kramers-Brillouin (WKB) approximation. Referring to the area instead of the electric field at individual points is shown to be a more robust approach in terms of numerical stability. The derived AE approach is implemented in an existing compact model for double-gate (DG) TFETs. In order to verify and show the numerical stability of this approach, modeling results are compared to TCAD Sentaurus simulation data for various sets of device parameters, whereby the simulations include both ON- and AMBIPOLAR-state of the TFET. In addition to the various device dimensions, the source material is also changed to demonstrate the feasibility of simulating hetero-junctions. Comparing the modeling approach with TCAD data shows a good match. Apart the limitations demonstrated and discussed in this paper, the main advantage of the AE approach is the simplicity and a better fit to TCAD data in comparison to the quasi-2D WKB approach.

3

System-level modeling of a Lab-On-Chip for micropollutants detection

Guiton S, Rezgui A, Madec M., Lallement C., Rufi F, Haiech J.

International Journal of Microelectronics and Computer Science

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2014

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Vol. 5, nr 3

116--125

EN

The issue addressed by this paper is system-level modeling of Lab-On-Chip (LOC) level. These microsystems integrate within a single chip many functions from several domains such as electronics, thermic, biochemistry or microﬂuidics. The modeling of these systems in a single environment and the interface between different domains is very challenging. In this paper, we propose some methods to model the entire system in VHDL-AMS. The models are developed and assembled from elementary building blocks, with a validation through experiments or numerical simulation on a reference tool, toward the complete LOC. For each domain, the modeling methodology is described. The principle is applied to a specific use case: a LOC designed for the detection of micro-pollutants in drinking water. It is based on the ELISA test leading to a pH-shift which is in turn detected by an Ion-Sensitive Field Effect Transistor (ISFET). In the last part of the paper, the ﬁrst results obtained with the complete zero-order model of the LOC are described. Of course, this model has to be improved in order to be faithful to the actual LOC but it will undoubtedly be a major asset for the optimization and reliability improvement of the LOC.

4

Model prądu drenu i pojemności w dwubramkowym tranzystorze MOS o krótkim kanale

Sawicka A., Łukasiak L., Jakubowski A., Tomaszewski D.

Elektronika : konstrukcje, technologie, zastosowania

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2011

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Vol. 52, nr 2

80-84

PL

Przedstawiono nowy model prądu drenu i pojemności w symetrycznym, niedomieszkowanym, dwubramkowym tranzystorze MOS. Model obejmuje wybrane efekty krótkiego kanału (zależność napięcia progowego od długości kanału, nasycenie prędkości nośników, modulacja efektywnej długości kanału i napięcia dren-żródło, wzrost gęstości ładunku w kanale indukowany napięciem drenu, obniżenie wysokości bariery indukowane napięciem drenu). Model zaimplementowano w języku opisu sprzętu Verilog-A, a jego dokładność została zweryfikowana w oparciu o symulacje przeprowadzone za pomocą pakietu ATLAS.

EN

A new model of drain current and capacitances in a symmetrical, undoped DG MOSFET is proposed. The new model includes several short-channel effects (dependence of threshold voltage on channel length, velocity saturation, effective channel-length and drain-source voltage modulation, drain-induced charge enhancement, drain induced barrier lowering). The model was implemented in Verilog-A Hardware Description Language. Its accuracy is verified by means of a comparison with ATLAS simulations.

5

Advanced compact modeling of the deep submicron technologies

Grabiński W., Bucher M., Sallese J.-M., Krummenacher F.

Journal of Telecommunications and Information Technology

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2000

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nr 3-4

31-42

EN

The technology of CMOS large-scale integrated circuits (LSI's) achieved remarkable advances over last 25 year and the progress is expected to continue well into the next century. The progress has been driven by the downsizing of the active devices such as MOSFETs. Approaching these dimensions, MOSFET characteristics cannot be accurately predicted using classical modeling methods currently used in the most common MOSFET models such as BSIM, MM9 etc, without introducing large number of empirical parameters. Various physical effects that needed to be considered while modeling UDSM devices: quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects, bias dependent source/drain resistances and capacitances, vertical and lateral doping profiles, etc. In this paper, we will discuss the progress in the CMOS technology and the anticipated difficulties of the sub-0.25 žm LSI downsizing. Subsequently, basic MOSFET modeling methodologies that are more appropriate for UDSM MOSFETs will be presented as well. The advances in compact MOSFET devices will be illustrated using application examples of the EPFL EKV model