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EN
This paper deals with the implementation of a DC and AC double-gate MOSFET compact model in the Verilog-AMS language for the transient simulation and the configuration of ultra low-power analog circuits. The Verilog-AMS description of the proposed model is inserted in SMASH circuit simulator for the transient simulation and the configuration of the Colpitts oscillator, the common-source amplifier, and the inverter. The proposed model has the advantages of being simple and compact. It was validated using TCAD simulation results of the same transistor realized with Silvaco Software.
EN
Shrinking gate length in conventional MOSFETs leads to increasing short channel effects like source-to-drain (SD) tunneling. Compact modeling designers are challenged to model these quantum mechanical effects. The complexity lies in the set-up between time efficiency, physical model relation and analytical equations. Multi-scale simulation bridges the gap between compact models, its fast and efficient calculation of the device terminal voltages, and numerical device models which consider the effects of nanoscale devices. These numerical models iterate between Poisson- and Schroedinger equation which significantly slows down the simulation performance. The physicsbased consideration of quantum effects like the SD tunneling makes the non-equilibrium Green’s function (NEGF) to a stateof-the-art method for the simulation of devices in the sub 10 nm region. This work introduces a semi-analytical NEGF model for ultra-short DG MOSFETs. Applying the closed-form potential solution of a classical compact model, the model turns the NEGF from an iterative numerical solution into a straightforward calculation. The applied mathematical approximations speed up the calculation time of the 1D NEGF. The model results for the ballistic channel current in DG-MOSFETs are compared with numerical NanoMOS TCAD [1] simulation data. Shown is the accurate potential calculation as well as the good agreement of the current characteristic for temperatures down to 75 K for channel lengths from 6 nm to 20 nm and channel thickness from 1.5 nm to 3 nm.
EN
A compact physical model of the Insulated Gate Bipolar Transistor has been presented. It has been based on the modular approach where the semiconductor structure is represented with several modules. The most important is the charge storage region where excess carriers are described with the ambipolar diffusion equation which enables obtaining carrier concentralion distribution along the wide, lightly doped base. In the future, it will enable implementing a dynamic device model. The model has been implemented in SPICE source code, which makes it accessible for the average electronic engineer.
PL
Przedstawiony został kompaktowy model fizyczny tranzystora IGBT. Jest on oparty na podejściu modułowym, w którym struktura półprzewodnikowa odzwierciedlona jest za pomocą szeregu modułów. Najistotniejszym z nich jest obszar składowania ładunku, w którym nośniki nadmiarowe opisane są równaniem dyfuzji ambipolarnej, które umożliwia otrzymanie rozkładu koncentracji nośników wzdłuż szerokiej, słabo domieszkowanej bazy. W przyszłości możliwa będzie implementacja dynamicznego modelu przyrządu. Model został zaimplementowany w kodzie źródłowym symulatora SPICE, co czyni go dostępnym dla przeciętnego inżyniera elektronika.
4
Content available Large-Signal RF Modeling with the EKV3 MOSFET Model
EN
This paper presents a validation of the EKV3 MOSFET model under load-pull conditions with high input power at 5.8 GHz, as well as S-parameter measurements with low input power up to 20 GHz. The EKV3 model is able to represent coherently the large- and small-signal RF characteristics in advanced 90 nm CMOS technology. Multifinger devices with nominal drawn gate length of 70 nm are used.
EN
An analysis of the measured macroscopic withinwafer variations for threshold voltage (Vth) and on-current (Ion) over several technology generations (180 nm, 100 nm and 65 nm) is reported. It is verified that the dominant microscopic variations of the MOSFET device can be extracted quantitatively from these macroscopic variation data by applying the surface-potential compact model Hiroshima University STARC IGFET model 2 (HiSIM2), which is presently brought into industrial application. Only a small number of microscopic parameters, representing substrate doping (NSUBC), pocket-implantation doping (NSUBP), carrier-mobility degradation due to gate-interface roughness (MUESR1) and channel-length variation during the gate formation (XLD) are found sufficient to quantitatively reproduce the measured macroscopic within-wafer variations of Vth and Ion for all channel length Lg and all technology generations. Quantitative improvements from 180 nm to 65 nm are confirmed to be quite large for MUESR1 (about 70%) and Lmin(XLD) (55%) variations, related to the gate-oxide interface and the gate-stack structuring, respectively. On the other hand, doping-related technology advances, which are reflected by the variation magnitudes of NSUBC (30%) and NSUBP (25%), are found to be considerably smaller. Furthermore, specific combinations of extreme microscopic parameter-variation values are able to represent the boundaries of macroscopic fabrication inaccuracies for Vth and Ion. These combinations are found to remain identical, not only for all Lg of a given technology node, but also for all investigated technologies with minimum Lg of 180 nm, 100 nm and 65 nm.
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