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1
Content available An Efficient Classification of Hyperspectral Remotely Sensed Data Using Support Vector Machine
Mahendra H. N., Mallikarjunaswamy S.
International Journal of Electronics and Telecommunications
|
2022
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Vol. 68. No. 3
609--617
EN
This work present an efficient hardware architecture of Support Vector Machine (SVM) for the classification of Hyperspectral remotely sensed data using High Level Synthesis (HLS) method. The high classification time and power consumption in traditional classification of remotely sensed data is the main motivation for this work. Therefore presented work helps to classify the remotely sensed data in real-time and to take immediate action during the natural disaster. An embedded based SVM is designed and implemented on Zynq SoC for classification of hyperspectral images. The data set of remotely sensed data are tested on different platforms and the performance is compared with existing works. Novelty in our proposed work is extend the HLS based FPGA implantation to the onboard classification system in remote sensing. The experimental results for selected data set from different class shows that our architecture on Zynq 7000 implementation generates a delay of 11.26 μs and power consumption of 1.7 Watts, which is extremely better as compared to other Field Programmable Gate Array (FPGA) implementation using Hardware description Language (HDL) and Central Processing Unit (CPU) implementation.
2
Obliczenia równoległe z wykorzystaniem GPU
Schubring T.
Logistyka
|
2014
|
nr 6
9405--9412
PL
W artykule przedstawiono wybrane aspekty przetwarzania równoległego w systemach zbudowanych na układach CPU(Central Processing Unit) i GPU(Graphical Procesing Unit) . Opisano równoległą architekturę obliczeniową CUDA (Compute Unified Device Architecture) oraz problemy związane z jej zastosowaniem i kopiowaniem danych z RAM CPU do RAM GPU. Omówiono ogólną koncepcję programu oraz jądra w języku C++ zbudowanego zgodnie z architekturą CUDA , odwołującego się do gridów, bloków i wątków. Przedstawiono przykłady układów graficznych przeznaczonych do przetwarzania równoległego HPC (High performance computing). Wskazano przykładowe zastosowania obliczeń GPGPU (General-Purpose computation on Graphics Processing Units). Zamieszczono spis dziedzin oraz przykłady aplikacji wykorzystujących GPGPU.
EN
The paper presents selected aspects of parallel processing systems built on the CPU (Central Processing Unit) and the GPU (Graphical Procesing Unit) systems. Describes parallel computing architecture CUDA ( Compute Unified Device Architecture ), and problems associated with its use and copying of data from from CPU RAM to GPU RAM. Discusses the general concept of the program and the kernel in C++ constructed in accordance with the CUDA architecture , referring to the grids , blocks and threads. The examples of graphics systems for HPC (High Performance Computing) parallel processing were presented. Sample calculations indicated use GPGPU (General-Purpose computation on Graphics Processing Units). Provide a list of fields and examples of applications using GPGPU.
3
Content available About Implementation of IEC 61131-3 IL Function Blocks in Standard Microcontrollers
Chmiel M., Mocha J., Hrynkiewicz E., Polok D.
International Journal of Electronics and Telecommunications
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2014
|
Vol. 60, No. 1
42-46
EN
The paper presents considerations on implementation of function blocks of the IL language, as fragments of control programs that use these blocks. Subsequently, the predefined function blocks of the IL language have been applied to implementation in a Central Processing Unit for a programmable controller based on standard microcontroller from such families as MCS-51, AVR and ARM with the Cortex-M3 core. The considerations refer to the IL language revision that is fully compliant with the IEC-61131-3 standards. The completed theoretical analysis demonstrated that the adopted method of the module description is really reasonable and offers substantial advantages as compared to direct calls of function modules already developed as subroutines. Also the executed experiments have proved the feasibility to arrange central units of programmable controllers on the basis of standard microcontrollers and such central units may be competitive to compact CPUs available on the market for typical PLCs.
4
Content available Xilinx Virtex-4 jako platforma rozwojowa jednostek centralnych PLC
Chmiel M., Mocha J., Hrynkiewicz E.
Pomiary Automatyka Kontrola
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2011
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R. 57, nr 1
55-57
PL
Artykuł prezentuje koncepcję platformy sprzętowo-programowej umożliwiającej testowanie różnych rozwiązań konstrukcyjnych jednostek centralnych sterowników programowalnych. Platforma do testowania jednostek bazuje na układzie FPGA Virtex-4 oraz opracowanym dedykowanym oprogramowaniu narzędziowym, umożliwiającym testowanie oraz badania właściwości opracowywanych jednostek. Przedstawiono wybrane dwuprocesorowe bitowo-bajtowe jednostki spotykane w literaturze, zorientowane na maksymalnie efektywne wykorzystanie obydwu procesorów. Szczególną uwagę zwrócono na szybkość wykonywania programu sterowania oraz funkcjonalność jednostki.
EN
To develop fast central processing units (CPUs) of programmable logic controllers (PLC) one can employ the architecture with two processors: a bit and a byte processor. The bit processor shall be responsible for processing the bit variables, while the byte processor shall be meant to deal with the byte (word) variables [1, 2, 3, 4, 5, 6]. In case of the double-processor architecture it is extremely important to synchronize operation of data exchange between the processors. The literature references report various synchronization methods [9, 10, 11, 12] that are described in Section 3. Sections 4 and 5 outline the combined hardware and software platform intended to enable testing and comparison between various architectures of CPUs. The presented solution employs a programmable FPGA module from the Virtex-4 family [7, 8], that are described in Section 2. The newly developed software enables compilation of application programs dedicated for the presented architecture. To develop programs for the presented solution the authors used the assembler-type programming language very similar to STL language that is normally applicable to STL controllers from Siemens [13, 14]. The software developed for PC computers make it possible to define new instructions for processors both on hardware and software levels (Fig. 1). The presented solution takes advantage of components that are typical for FPGA modules, such as BockRAM memory units (Fig. 2). The presented platforms enable further research and development efforts intended to design fast CPUs for programmable logic controllers.
5
Content available remote Concurrent operation of processors in the bit-byte CPU of a PLC
Chmiel M., Hrynkiewicz E.
Control and Cybernetics
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2010
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Vol. 39, no 2
559-579
EN
The paper presents some selected hardware solutions for the PLC dual processor bit-byte CPUs, which are oriented at optimised data exchange between the CPU processors. The optimisation aims at maximum utilisation of capabilities of the two-processor architecture of the CPU. The key point is preserving high speed of instruction processing by the bit-processor, and high functionality of the byte-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimise the situations, when one processor has to wait for the other.
6
Content available remote Możliwości i perspektywy współczesnej grafiki komputerowej
Szuba T.
Roczniki Geomatyki
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2009
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T. 7, z. 6
97-103
EN
The paper deals with the problem: what is modern computer graphics now and what is its potential. If we think in terms of .the centre of gravity., modern computer graphics is moving from the art towards capturing the essence of an object or a being to be modeled. In other words, key problems for the computer graphics are physical phenomena (e.g. liquids), mechanical properties (e.g. textile, hairs) or even mental properties of virtual beings. Therefore, modern computer graphics requires extremely high computational abilities. Advanced computer games demonstrate this very well. Having all this in mind, many researchers think that modern computer graphics is the main leading force in the development of modern computer science. On the basis of above remarks, the paper tries to resume the application areas of modern computer graphics now and in the near future.
7
Content available remote Fast Operating PLC Based on Event-Driven Control Program Tasks Execution
Chmiel M., Hryniewicz E., Milik A.
Electronics and Telecommunications Quarterly
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2009
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Vol. 55, No 2
269-286
EN
The paper presents modified idea of program execution in PLCs. Instead of serial cyclic execution of control program event-driven execution is proposed. Suggested approach to program execution allows for selective execution of program parts or tasks. Only these blocks from entire program are executed whose variables have changed since last calculation. Proposed method can be implemented as software modification or as hardware accelerated solution. The most important part of the idea is task or subprogram triggering condition computation. Methods of program optimization are discussed. In order to determine program blocks that require recalculation in current program scan execution specific hardware support is planned to be researched. Memory content change detection unit allows to determine changes in memory content since last program block execution.
8
Content available remote ALPHA XL
Panasiewicz A.
Napędy i Sterowanie
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2002
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R. 4, nr 9
54--58
PL
W sierpniu br. użytkownicy sterowników logicznych otrzymają do swojej dyspozycji zupełnie nowy system oparty o jednostkę centralną ALPHA XL. Sterownik ten produkowany będzie równolegle z popularną wersją o nazwie ALPHA. Projektując nowy model ALPHA XL, Mitsubishi Electric zachowało funkcjonalność programową modelu ALPHA.
9
Content available remote An approach to natural language processing in computer system
Ratyńska J.
Journal of Applied Computer Science
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2001
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Vol. 9, nr 1
33-41
EN
In the paper there has been presented natural language processing system as an example of the system based on natural Polish language. The system is provided in dialogue generator based on grammatical processor. That processor is responsible for identification and interpretation of information introduced by the user into the computer system considering grammatical level. The main task of that processor is grammatical identification and interpretation of metalanguage variable being the elements of user's utterance. That natural language processing system can find practical application for communication between user and computer.
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