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1 Electronics and Telecommunications Quarterly

1 2008

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FPGA implementation of a lossless to lossy bitonal image compression system

Savakis A., Lukowiak M., Pyle J.

Electronics and Telecommunications Quarterly

2008

Vol. 54, No 4

533-546

This paper presents an FPGA implementation of a lossless to lossy image compression system that incorporates region of interest processing. Block Arithmetic Coder Image Compression is combined with Low-Latency Greedy Flipping Utilizing Forgetful Error Diffusion for loss introduction. The approach allows for perfect quality, associated with lossless compression, or three levels of reduced image quality, high, medium and low, associated with various levels of loss introduction. Region of interest processing can be incorporated by adjusting the system parameters for maximum visual benefit. The overall system was successfully realized on a Virtex FPGA platform.