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1

Improving LUT count of FPGA-based sequential blocks

Barkalov Alexander, Titarenko Larysa, Mazurkiewicz Małgorzata, Krzywicki Kazimierz

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2021

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Vol. 69, nr 2

art. no. e136728

EN

Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and consumed energy. The paper proposes a novel technology-dependant design method targeting LUT-based Mealy FSMs. It belongs to the group of structural decomposition methods. The method is based on encoding the product terms of Boolean functions representing the FSM circuit. To diminish the number of LUTs, a partition of the set of internal states is constructed. It leads to three-level logic circuits of Mealy FSMs. Each function from the first level requires only a single LUT to be implemented. The method of constructing the partition with the minimum amount of classes is proposed. There is given an example of FSM synthesis with the proposed method. The experiments with standard benchmarks were conducted. They show that the proposed method can improve such FSM characteristics as the number of used LUTs. This improvement is accompanied by a decrease in performance. A positive side effect of the proposed method is a reduction in power consumption compared with FSMs obtained with other design methods.

2

Hardware reduction for LUT-based mealy FSMs

Barkalov A., Titarenko L., Mielcarek K.

International Journal of Applied Mathematics and Computer Science

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2018

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Vol. 28, no. 3

595--607

EN

A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each state has two codes. It diminishes the number of arguments in input memory functions. An example of synthesis is given, along with results of investigations. The method targets rather complex FSMs, having more than 15 states.

3

Synteza automatu Mealy’ego z wbudowanym blokiem pamięci w strukturach programowalnych

Kołopieńczyk M., Barkalov A., Titarenko L.

Przegląd Elektrotechniczny

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2013

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R. 89, nr 11

109-113

PL

W artykule zostanie przedstawiona metoda umożliwiająca syntezę skończonego automatu stanów typu Mealy’ego z wbudowanym blokiem pamięci (ang. Embedded Memory Blocks, EMB) w strukturach programowalnych typu FPGA. Metoda ta bazuje na przekształceniu strukturalnej tabeli przejść skończonego automatu stanów oraz na kodowaniu elementów podzbioru warunków logicznych. W artykule zostanie zaprezentowany przykład projektowania oraz wstępne wyniki badań.

EN

In this article we propose a method allowing implementing Mealy FSM logic circuits with embedded memory blocks of FPGA chips. The method is based on transformation of FSM structure table and replacement of some logical conditions. Example of design and preliminary results of investigations are given.

4

On representation of a semidirect product of cyclic groups by a 2-state time-varying mealy automaton

Woryna A.

Zeszyty Naukowe. Matematyka - Fizyka / Politechnika Śląska

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2004

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z. 91

343-354

EN

We present thesubgroup K - [W, W].Z of the wreath product W = Zlx0Z relative to an n-element set X0 as a group generated by a 2-state time-varying Mealy automaton. The action of K on the sets of finite and infinite words over the changing alphabet we study.

PL

W splocie W = Z I x0 Z względem n-elementowego zbioru X 0 rozważamy podgrupę K = [W, W]. Z jako grupę generowaną przez zmienny w czasie automat Mealy'ego o dwóch stanach. Badamy działanie grupy K na zbiorach słów skończonych i nieskończonych nad zmiennym alfabetem.

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Odwzorowania określone za pomocą automatów Mealy'ego zmiennych w czasie

Woryna A.

Zeszyty Naukowe. Automatyka / Politechnika Śląska

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2003

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z. 138

201-215

EN

From among many articles concerning the automata as transducers most of them describe direct automata which have the same structure in all the moments of the discrete time scale or the time varying automata with a fixed alphabet. The extensive presentation of the knowledge on the mentioned above automata includes a monograph [12]. The given work generalizes the idea of time varying automata allowing for a possibility of change of the alphabet itself in the consecutive tacts of the automaton's work; the transformations generated by these automata are defined and described. In particular the transformations generated by two of the most important time varying automata are described namely periodic automata as well as permutation automata.