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1

Universal Computation in a Simplified Brownian Cellular Automaton with von Neumann Neighborhood

Xu Wen-Li, Lee Jia, Chen Hui-Hui, Isokawa Teijiro

Fundamenta Informaticae

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2019

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Vol. 165, nr 2

139--156

EN

A Brownian cellular automaton (BCA) is an asynchronous cellular automaton (ACA) in which local configurations representing signals may move forth and back randomly, as if they were undergoing random walks. The random fluctuation offers a natural mechanism to propagate signals in the 2-dimensional cell space, and to cross signals moving in directions perpendicular to each other. As a result, the BCA in (Lee et al., 2016) employs 4 cell states and 17 transition rules to conduct universal computation, both of which are less than other equivalent ACAs in the literature. This paper aims to advance the fluctuation-based scheme one step further, via proposing a new BCA with 4 states and 14 rules that achieves a reduction in the number of transition rules. We show that the BCA is capable of implementing any arbitrary logic circuit, thereby proving its universality in computation. We illustrate this by implementing a circuit that converts a 4-bit number to its equivalent hexadecimal digit.

2

Persistent and Nonviolent Steps and the Design of GALS Systems

Fernandes J., Koutny M., Mikulski Ł, Pietkiewicz-Koutny M., Sokolov D., Yakovlev A.

Fundamenta Informaticae

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2015

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Vol. 137, nr 1

143--170

EN

A concurrent system is persistent if throughout its operation no activity which became enabled can subsequently be prevented from being executed by any other activity. This is often a highly desirable (or even necessary) property; in particular, if the system is to be implemented in hardware. Over the past 40 years, persistence has been investigated and applied in practical implementations assuming that each activity is a single atomic action which can be represented, for example, by a single transition of a Petri net. In this paper we investigate the behaviour of GALS (Globally Asynchronous Locally Synchronous) systems in the context of VLSI circuits. The specification of a system is given in the form of a Petri net. Our aim is to re-design the system to optimise signal management, by grouping together concurrent events. Looking at the concurrent reachability graph of the given Petri net, we are interested in discovering events that appear in ‘bundles’, so that they all can be executed in a single clock tick. The best candidates for bundles are sets of events that appear and re-appear over and over again in the same configurations, forming ‘persistent’ sets of events. Persistence was considered so far only in the context of sequential semantics. In this paper, we move to the realm of step based execution and consider not only steps which are persistent and cannot be disabled by other steps, but also steps which are nonviolent and cannot disable other steps. We then introduce a formal definition of a bundle and propose an algorithm to prune the behaviour of a system, so that only bundled steps remain. The pruned reachability graph represents the behaviour of a re-engineered system, which in turn can be implemented in a new Petri net using the standard techniques of net synthesis. The proposed algorithm prunes reachability graphs of persistent and safe nets leaving bundles that represent maximally concurrent steps.

3

Projektowanie układów asynchronicznych z wykorzystaniem środowiska BALSA

Stachańczyk D.

Przegląd Elektrotechniczny

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2012

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R. 88, nr 11b

87-89

PL

W artykule przedstawiono wybrane zagadnienia związane z projektowaniem systemów asynchronicznych, najważniejsze zalety tego typu układów w porównaniu do układów synchronicznych oraz praktyczne przykłady ich implementacji. Przedstawione zostały również przykłady najważniejszych narzędzi wspomagających proces projektowania układów asynchronicznych. W artykule przedstawiono dokładniej środowisko BALSA oraz wyniki doświadczeń i prób implementacji wybranych układów asynchronicznych z wykorzystaniem tego środowiska.

EN

The paper presents selected issues related to the asynchronous systems design, the most important advantages of such systems in comparison to synchronous circuits, and practical examples of their implementation. The paper includes also the description of best know EDA tools supporting asynchronous circuit design, including BALSA design environment. The BALSA design environment was used to implement some asynchronous circuits in FPGA structure and the experimental results and conclusion are also included in this paper.

4

Asynchronous circuits through systemC description

Damavandpeyma M., Mohammadi S.

Electronics and Telecommunications Quarterly

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2008

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Vol. 54, No 4

493-505

EN

Asynchronous design is fundamentally different and not yet a well-established methodology. An important obstacle to growth of this methodology is lack of CAD tools to design circuit automatically. The starting point in developing a circuit is its modeling and simulation. At this paper we will propose an asynchronous library as extension to SystemC language to enable asynchronous circuit description at the highest level of abstraction. For this purpose, channel, join, fork, mux, demux, and merge that are basic elements of asynchronous circuits are introduced into the library. Also a tool was developed which extracts optimized control flow graph and data flow graphs from the high level description. By using proposed library modeling and designing of efficient asynchronous circuits can be done without having to deal with detail of asynchronous implementations. Extracted CFG and DFG were prepared in well-defined form that can easily be used for synthesis purpose, verification or test generation in later steps of our digital design flow.