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1 International Journal of Electronics and Telecommunications

1 2014

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Design of an Ultra-Low Power CT Σ∆ A/D Modulator in 65nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation

Wang Y., Cai H.

International Journal of Electronics and Telecommunications

2014

Vol. 60, No. 1

109-115

A high performance, ultra-low power, fully differentia 2nd-order continuous-time Σ∆ analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182nA from a 1.2V power supply, meeting the ultra-low power requirement of the cardiac pacemaker applications. A 65nm CMOS technology is employed to implement the Σ∆ modulator. The modulator achieves a simulated SNR of 53.8dB over a 400 Hz signal bandwidth, with 32KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45×0.50mm².