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4 Prace Przemysłowego Instytutu Elektroniki

4 1998

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Oversampling sigma-delta analog-to-digital converters modeling based on VHDL

Baraniecki R., Dąbrowski P., Hejn K.

Prace Przemysłowego Instytutu Elektroniki

1998

nr 132

163-171

The paper presents a VHDL model of an oversampling sigma-delta analog-to-digital converter created on the behavioral hierarchy level. Although VHDL has been primarily devoted to digital circuit design, it can also be applied to certain mixed-signal circuits. The model of the analog part is as simple as possible and includes only necessary parameters that enable to determine the potential resolution of a converter. The model of the digital parttis described in the synthesizable subset of VHDL and parameterized according to the word length and the type of arithmetic applied. The validation process of the converter model is also shown. It is performed by a VHDL simulator and a postprocessor tool enabling to carry out FFT. Simulation results enclosed prove the efficiency of the design approach presented.

Comparative evaluation of delta-sigma modulator structures used in the oversampling A/D converters

Hejn K., Kale I., Kurek A.

Prace Przemysłowego Instytutu Elektroniki

1998

nr 132

35-40

The work reported in this paper focuses on computer simulations of Delta-Sigma modulators for oversampling Analog-to-Digltal (AD) converters. It calls into question the efficacy of traditional additive white noise techniques for modeling and analyzing the asymptotic statistical properties of quantization errors that arise in single and multistage oversampling modulators. The potential of the Comdisco - SPW on the SunSPARCl platform has been utilized for estimating gain error commonly used for data acquisition AD converters. It has been shown that the cascaded structure (type delta-sigma11 consisting of two first-order modulators) works much better than the common second-order modulator (type delta-sigma). The simulations results obtained have exhibited that the cascaded structure (type delta-sigma) with differential first-order modulators has the potential of 20 bit amplitude resolution within acoustic signal bandwidth.

A design technique for polyphase decimators with binary constrained coefficients for high resolution A/D converters

Krukowski A., Kale I., Morling R., Hejn K.

Prace Przemysłowego Instytutu Elektroniki

1998

nr 132

53-56

This paper presents a design technique for liigh fidelity multistage decimation filters based on the polyphase and decimator structures presented in [1][2], catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Converter (ADC) applications in excess of 16 bit resolution. The resulting filter coefficients are constrained to the required bit length using a "bit tipping algorithm" [3]. This technique is comparatively presented through an example of a cascaded decimation filter, designed for a 20-bit resolution ADC and compared to with other approximation methods. The coefficients and frequency responses of the cascaded filler are reported.

A "bit-flipping" approach to multistage two-path decimation filter design

Krukowski A., Kale I., Cain G., Hejn K.

Prace Przemysłowego Instytutu Elektroniki

1998

nr 132

42-51

This paper presents a design technique for high fidelity multistage decimation filters based on the polyphase decimator structures presented by Constantinides et al, catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Convener (ADC) applications in excess of 16-bit resolution. The resulting filter coefficients are constrained to the required bit length using a "bit-flipping algorithm" This technique illustrated in the context of an example of a cascaded decimation filter, designed for a 20-bit resolution ADC. and compared to other approximation methods. The resulting coefficient values and frequency responses of the cascaded filters are reported