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1

A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology

Khatak Anil, Kumar Manoj, Dhull Sanjeev

International Journal of Electronics and Telecommunications

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2021

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Vol. 67, No. 3

347--354

EN

A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 mega-samples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.

2

Woltomierz cyfrowy z przetwornikiem 24-bitowym AD7767

Rudnicki T.

Wiadomości Elektrotechniczne

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2011

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R. 79, nr 9

74-76

PL

Przedstawiono projekt oraz analizę dokładności układu woltomierza cyfrowego napięcia stałego z przetwornikiem analogowo-cyfrowym 24-bitowym.

EN

The paper presents a design and accuracy of digital dc voltmeter with 24 bit analog to digital converter.

3

On the bias of terminal based gain and offset estimation using the ADC histogram test method

Correa Alegria F., Tiglao N. M. C.

Metrology and Measurement Systems

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2011

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Vol. 18, nr 1

3-12

EN

The Histogram Test method is a popular technique in analog-to-digital converter (ADC) testing. The presence of additive noise in the test setup or in the ADC itself can potentially affect the accuracy of the test results. In this study, we demonstrate that additive noise causes a bias in the terminal based estimation of the gain but not in the estimation of the offset. The estimation error is determined analytically as a function of the sinusoidal stimulus signal amplitude and the noise standard deviation. We derive an exact but computationally difficult expression as well as a simpler closed form approximation that provides an upper bound of the bias of the terminal based gain. The estimators are validated numerically using a Monte Carlo procedure with simulated and experimental data.

4

Software for data acquisition AMC module with PCI express interface

Szachowałow S., Jabłoński G., Sakowicz B., Makowski D., Butkowski Ł., Koprek W., Simrock S.

International Journal of Microelectronics and Computer Science

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2010

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Vol. 1, nr 1

95-98

EN

Free Electron Laser in Hamburg (FLASH) and X-Ray Free Electron Laser (XFEL) are linear accelerators that require a complex and accurate Low Level Radio Frequency (LLRF) control system. Currently working systems are based on aged Versa Module Eurocard (VME) architecture. One of the alternatives for the VME bus is the Advanced Telecommunications and Computing Architecture (ATCA) standard. The ATCA based LLRF controller mainly consists of a few ATCA carrier boards and several Advanced Mezzanine Cards (AMC). AMC modules are available in variety of functions such as: ADC, DAC, data storage, data links and even CPU cards. This paper focuses on the software that allows user to collect and plot the data from commercially available TAMC900 board.