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An analog linear SVM image classifier

Festila L., Szolga L. A., Groza R., Hintea S., Cirlugea M.

Journal of Automation Mobile Robotics and Intelligent Systems

2009

Vol. 3, No. 2

82-87

A linear Support Vector machine classifier is proposed in this paper. In such SVM architectures based on multiplying laws the main building blocks are multipliers. We propose in this paper multiplying and weighting cells, developed by using a model consisting of a compound of two inverse non-linear functions. This procedure is suitable for VLSI implementation because it permits the use of simple nonlinearized standard log-domain or DA cells that compensate each other nonlinearities to obtain an extended domain of operation. Current-mode ELIN (externally linear internally nonlinear) design is used for its low voltage, low power and high speed characteristics. The resulted parallel-serial classifier was simulated taking into account real parameters of transistors in BICMOS technology.

Design of a 3.3V Four-Quadrant Analog CMOS Multiplier

Szczepański S., Kozieł S.

Bulletin of the Polish Academy of Sciences. Technical Sciences

2003

Vol. 51, nr 2

163-172

The two CMOS four-quadrant analog multipliers that can operate from a supply voltage of 3.3V are presented. The proposed circuit technique has been developed using MOS transistors working both in saturation and nonsaturation regions. Simulation results have shown that the introduced circuit based on MOS devices operating in the linear region has the total harmonic distortion (THD) less than 0.75% for input signal up to 2Vpp with 10MHz sine wave. A 3-dB bandwidth about 1GHz is attainable from either input. A power consumption of the circuit is 1.4mW.