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Analog circuits specification driven testing by the means of digital stream and non-linear estimation model optimized evolutionarily

Golonek T., Chruszczyk Ł.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2020

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Vol. 68, nr 6

1283--1299

EN

The method described in this work allows to determine the optimal distribution of pulses of digital signal as well as the non-linear mathematical model based on a multiple regression statistical analysis, which are specialized to an effective and low-cost testing of functional parameters in analog electronic circuits. The aim of this concept is to simplify the process of analog circuit specification validation and minimize hardware implementation, time and memory requirements during the testing stage. This strategy requires simulations of the analyzed analog electronic circuit; however, this effort is done only once – before the testing stage. Then, validation of circuit specification can be obtained after a quick, very low-cost procedure without time consuming computations and without expensive external measuring equipment usage. The analyzed test signature is a time response of the analog circuit to the stream of digital pulses for which distributions were determined during evolutionary optimization cycles. Besides, evolutionary computations assure determination of the optimal form and size of the non-linear mathematical formula used to estimate specific functional parameters. Generally, the obtained mathematical model has a structure similar to the polynomial one with terms calculated by means of multiple regression procedure. However, a higher ordered polynomial usage makes it possible to reach non-linear estimation model that improves accuracy of circuit parametric identification. It should be noted that all the evolutionary calculations are made only at the before test stage and the main computational effort, for the analog circuit specification test design, is necessary only once. Such diagnosing system is fully synchronized by a global digital signal clock that precisely determines time points of the slopes of input excitation pulses as well as acquired output signature samples. Efficiency of the proposed technique is confirmed by results obtained for examples based on analog circuits used in previous (and other) publications as test benchmarks.

2

Heuristic methods to test frequencies optimization for analogue circuits diagnosis

Jantos P., Grzechca D., Golonek T., Rutkowski J.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2008

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Vol. 56, nr 1

29-38

EN

This paper presents methods for optimal test frequencies search with the use of heuristic approaches. It includes a short summary of the analogue circuits fault diagnosis and brief introductions to the soft computing techniques like evolutionary computation and the fuzzy set theory. The reduction of both, test time and signal complexity are the main goals of developed methods. At the before test stage, a heuristic engine is applied for the principal frequency search. The methods produce a frequency set which can be used in the SBT diagnosis procedure. At the after test stage, only a few frequencies can be assembled instead of full amplitude response characteristic. There are ambiguity sets provided to avoid a fault tolerance masking effect.

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Wykorzystanie neuronowych sieci modularnych do diagnostyki analogowych układów elektronicznych

Kurowski I., Rutkowski J.

Elektronika : konstrukcje, technologie, zastosowania

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2007

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Vol. 48, nr 11

37-39

PL

Przedmiotem artykułu jest system diagnostyczny służący do lokalizacji pojedynczych uszkodzeń analogowych układów elektronicznych. Na etapie przedtestowym dla diagnozowanego układu elektronicznego skonstruowano słownik uszkodzeń na podstawie symulacji komputerowych dla każdego analizowanego stanu obwodu. Jako pobudzenie wykorzystano zarówno zasilanie układu, jak i podawany na wejście obwodu sygnał sinusoidalny. Na wyjściu badanego obwodu mierzono moduł i fazę napięcia. Zespół dwóch sieci neuronowych o radialnych funkcjach bazowych został użyty jako klasyfikator uszkodzeń (katastroficznych i parametrycznych). Odpowiedź końcową dwóch równolegle połączonych sieci neuronowych wyznaczono z wykorzystaniem przestrzeni BKS (Behavior Knowledge Space).

EN

This paper presents a diagnostic system created for localization of faults in analog electronic circuits. The system is based on dictionary method. As stimu oflation signals, dc supply voltage and sinusoidal input signal have been used. The frequency of sinusoidal signal is variable. Voltages and phases in output of the circuit are measured to create dictionary of faults. Radial Basis Function (RBF) neural networks were used as neural classifiers. Behavior Knowledge Space (BKS) was used to find the optimum final answer of parallel classifiers. Software which has been used to generate teaching-testing files had been created in Borland Delphi. Simulations of electronic circuits have been realized by SPICE. Software, used to simulate neural classifiers has been created in Matlab.

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Finding of optimal excitation signal for testing of analog electronic circuits

Chruszczyk L., Grzechca D., Rutkowski J.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2007

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Vol. 55, nr 3

273-280

EN

This article presents combined approach to analog electronic circuits testing by means of evolutionary methods (genetic algorithms) and using some aspects of information theory utilisation and wavelet transformation. Purpose is to find optimal excitation signal, which maximises probability of fault detection and location. This paper fo-cuses on most difficult case where very few (usually only input and output) nodes of integrated circuit under test are available.

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Wejściowo-wyjściowa metoda detekcji uszkodzeń w elektronicznych układach analogowych uwzględniająca tolerancje elementów

Czaja Z.

Diagnostyka

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2004

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Vol. 30, T. 1

119--122

PL

W artykule przedstawiono nowe podejście detekcji i lokalizacji uszkodzeń w elektronicznych układach analogowych z uwzględnieniem tolerancji elementów. Składa się ono z dwóch etapów. W pierwszym etapie tworzony jest słownik uszkodzeń składający się z opisu elipsy aproksymującej obszar nominalny reprezentujący brak uszkodzeń i współczynników określających szerokość pasów lokalizacyjnych. Zaprezentowano nowy algorytm tworzenia takiej elipsy i algorytm wyznaczania szerokości pasa lokalizacyjnego. W drugim etapie omówiono algorytm detekcji i lokalizacji uszkodzeń.

EN

In the paper a new approach of fault detection and localisation of analog electronic circuits taking into consideration tolerances of elements is described. It consists of two stages. In the first stage a fault dictionary consisting of description of an ellipse, which approximates a nominal area representing a fault-free circuit, and coefficients defining widths of localisation bells are created. A new algorithm of generation of the ellipse and the algorithm of determination of the width of localisation bell are presented. In the second stage the algorithm of fault detection and localisation is described.