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1

Comparative analysis of low power implementation for AES algorithm in ARTIX 7 FPGA & ASIC

Manoj G., Roopa Jayasingh J., Divya P. S., Saravanan K.

Przegląd Elektrotechniczny

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2023

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R. 99, nr 6

23--26

EN

Encryption is a mandate in today’s information sharing based society. Various Algorithms have been proposed and used to implement encryption. The AES algorithm is one such encryption algorithm widely known for its faster encryption speeds and withstanding ability against cyberattacks. Its resilience comes from the fact that it can use 128 or 192- or 256-bit keys to encrypt 128, 192 or 256 bit plain text. The AES algorithm has been implemented in ASIC and FPGA to realize the best practices for the implementation of the algorithm for efficient usage. The power, area and timing analysis from both implementations have been compared to infer the best implementation strategy. The experimental results indicate that care has to be taken to reduce switching activity of signals which were observed to be the primary contributor of dynamic power consumption. Recommendations have been included to reduce signal switching power consumption during Logic BIST designs for the algorithm. The power analysis show that ASIC implementation of the AES algorithm would be much more beneficial in comparison to ARTIX 7 FPGA implementation.

PL

Szyfrowanie jest obowiązkiem w dzisiejszym społeczeństwie opartym na wymianie informacji. Zaproponowano i wykorzystano różne algorytmy do implementacji szyfrowania. Algorytm AES jest jednym z takich algorytmów szyfrowania, powszechnie znanym z większej szybkości szyfrowania i odporności na cyberataki. Jego odporność wynika z faktu, że może używać kluczy 128-, 192- lub 256-bitowych do szyfrowania zwykłego tekstu 128, 192 lub 256-bitowego. Algorytm AES został zaimplementowany w ASIC i FPGA, aby zrealizować najlepsze praktyki implementacji algorytmu w celu efektywnego wykorzystania. Porównano analizę mocy, obszaru i czasu z obu wdrożeń, aby wywnioskować najlepszą strategię wdrożenia. Wyniki eksperymentów wskazują, że należy zwrócić uwagę na zmniejszenie aktywności przełączania sygnałów, które były głównymi sprawcami dynamicznego poboru mocy. Uwzględniono zalecenia dotyczące zmniejszenia poboru mocy przy przełączaniu sygnału podczas projektowania logiki BIST dla algorytmu. Analiza mocy wykazała, że implementacja ASIC algorytmu AES byłaby dużo bardziej korzystna w porównaniu z implementacją ARTIX 7 FPGA.

2

Program for Simulation and Testing of Apply Cryptography of Advance Encryption Standard (AES) Algorithm with Rivest-Shamir-Adleman (RSA) Algorithm for Good Performance

Pattanavichai Santi

International Journal of Electronics and Telecommunications

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2022

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Vol. 68. No. 3

475--481

EN

Nowadays, information security management systems are important parts of managing a system for better handling of the information security. In scenarios and situations where safety management is done by managing protection of malwares, it is important to manage security issues properly. Cryptography is an approach which makes possible for a recipient to encrypt and decrypt the information. A combination of two different strategies for encryption and decryption in the text encoding will be transformed into the used all content. The encryption and decryption key of the content decryption key is used. There are different types of information. A number, such as finding two large prime numbers with that product. The number, the size of the RSA key is large enough to make, it's hard to pinpoint these numbers. The key, known as the RSA public key, is the most prominent open encryption. Calculations were used for information exchange. In this paper, we created a program for simulation and testing of apply cryptography of Advance Encryption Standard (AES) algorithm with Rivest-Shamir-Adleman (RSA) algorithm for better performance. In this study, this program is an application of a new algorithm to be the AES&RSA principle of using a public key instead of a private key for cryptography, and the testing of encryption and decryption for the AES&RSA algorithm resulted in time is no different on the AES algorithm and more secure encryption and decryption. The results indicated that the time needed for encoding and decoding of AES&RSA algorithm has been reduced (i.e., efficiency has been improved).

3

Image compression and encryption algorithm based on advanced encryption standard and hyper-chaotic system

Nie Zhe, Liu Zheng-Xin, He Xiang-Tao, Gong Li-Hua

Optica Applicata

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2019

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Vol. 49, nr 4

545--558

EN

An image compression and encryption algorithm by combining the advanced encryption standard (AES) with the hyper-chaotic system is designed, in which Arnold map is employed to eliminate part of the block effect in the image compression process. The original image is compressed with the assistance of a discrete cosine transform and then its transform coefficients are encrypted with the AES algorithm. Besides, the hyper-chaotic system is adopted to introduce the nonlinear processfor image encryption. Numerical simulations and theoretical analyses demonstrate that the proposed image compression and encryption algorithm is of high security and good compression performance.

4

Wykorzystanie algorytmu AES w technologii RFID

Waśniewski T., Szymonik A.

Gospodarka Materiałowa i Logistyka

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2014

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nr 5

651--668

PL

Identyfikacja radiowa towarów w systemie logistycznym to nowa technologia dynamicznie rozwijająca się, która przynosi ogromne korzyści wydajności pracy oraz pozwala zautomatyzować wiele procesów logistycznych. W artykule przedstawiono problem dotyczący bezpieczeństwa i prywatności danych wymienianych poprzez systemy RFID. Wskazano potrzeby rozwiązania symetrycznego, uwierzytelniania dla systemu RFID przy zastosowaniu niewielkich matryc i niskiego poboru mocy. Opisano możliwości implementacji algorytmu AES w metkach RFID.

EN

Radio frequency identification of goods in the logistics system is a new technology rapidly growing, which brings enormous productivity benefits and automates many of the processes of logistics. Presents a problem with the security and privacy of data exchanged via RFID systems. Presents the problem of solutions symmetric authentication for RFID using small matrices and low power consumption. Describes the possibilities of implementation of the AES algorithm in RFID tags.

5

Security characterisation of a hardened AES cryptosystem using a laser

Roscian C., Praden F., Dutertre J. M., Fournier J., Tria A.

Technical Sciences / University of Warmia and Mazury in Olsztyn

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2012

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nr 15(1)

139-154

EN

The AES is a standard encryption algorithm used in numerous cryptographic systems like smart cards, TPMs as well as in protocols like WPA2 or OpenSSL. Measuring the robustness of AES implementations against physical attacks is of utmost import-ance in order to guarantee the security of the system into which the AES is used. In this article, we describe how a hardware AES, embedding countermeasures against physical attacks, has been characterized using a laser. With the latter, we tried to implement a class of physical attacks called fault attacks which, when successful, allows an attacker to retrieve the secret key used by the AES module. Our experiments have allowed us to validate the efficiency of some of the countermeasures implemented in this AES implementation and have given us hints on how to further improve them.

PL

AES to standardowy algorytm szyfrowania stosowany w wielu systemach kryptograficznych, np. kartach elektronicznych, TPM, oraz takich protokołach, jak WPA2 czy OpenSSL. Pomiar odporności implementacji algorytmu AES na ataki fizyczne jest najważniejszy do zapewnienia bezpieczeństwa systemowi opartemu na AES. W artykule opisano, jak sprzętowa implementacja AES z wbudowanymi zabezpieczeniami przeciwko fizycznym atakom była badana z wykorzystaniem lasera. Następnie podjęto próby zaimplementowania ataków fizycznych polegających na wstrzykiwaniu błędów; ataki te - zakończone sukcesem - pozwalają atakującemu na przechwycenie tajnego klucza wykorzystywanego w module AES. Przeprowadzone eksperymenty pozwoliły na sprawdzenie efektywności zabezpieczeń zaimplementowanych w module sprzętowym AES oraz wskazały możliwości dalszego podniesienia poziomu bezpieczeństwa.

6

Cryptanalysis of the Full AES Using GPU-Like Special-Purpose Hardware

Biryukov A., Großschädl J.

Fundamenta Informaticae

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2012

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Vol. 114, nr 3/4

221-237

EN

The block cipher Rijndael has undergone more than ten years of extensive cryptanalysis since its submission as a candidate for the Advanced Encryption Standard (AES) in April 1998. To date, most of the publicly-known cryptanalytic results are based on reduced-round variants of the AES (respectively Rijndael) algorithm. Among the few exceptions that target the full AES are the Related-Key Cryptanalysis (RKC) introduced at ASIACRYPT 2009 and attacks exploiting Time- Memory-Key (TMK) trade-offs such as demonstrated at SAC 2005. However, all these attacks are generally considered infeasible in practice due to their high complexity (i.e. 2^99.5 AES operations for RKC, 2^80 for TMK). In this paper, we evaluate the cost of cryptanalytic attacks on the full AES when using special-purpose hardware in the form of multi-core AES processors that are designed in a similar way as modern Graphics Processing Units (GPUs) such as the NVIDIA GT200b. Using today's VLSI technology would allow for the implementation of a GPU-like processor reaching a throughput of up to 10^12 AES operations per second. An organization able to spend one trillion US$ for designing and building a supercomputer based on such processors could theoretically break the full AES in a time frame of as little as one year when using RKC, or in merely one month when performing a TMK attack. We also analyze different time-cost trade-offs and assess the implications of progress in VLSI technology under the assumption that Moore’s law will continue to hold for the next ten years. These assessments raise some concerns about the long-term security of the AES.