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High Performance DIF-FFT Using Dissimilar Partitioned LUT Based Distributed Arithmetic

Cheepurupalli Kusma Kumari, Charan Muntha, Rao Jammu Bhaskara, Noor Mahammad S.

International Journal of Electronics and Telecommunications

2021

Vol. 67, No. 4

631--637

Real-time data processing systems utilize Digital Signal Processing (DSP) functions as the base modules. Most of the DSP functions involve the implementation of Fast Fourier Transform (FFT) to convert the signals from one domain to another domain. The major bottleneck of Decimation in frequency - Fast Fourier Transform (DIF-FFT) implementation lies in using a number of Multipliers. Distributed arithmetic (DA) is considered as one of the efficient techniques to implement DIF-FFT. In this approach, the multipliers are not used. The proposed technique exploits the very advantage of the look-up table by storing the Twiddle factors, thereby avoiding the multipliers required in the butterfly structure. DIF-FFT using Distributed Arithmetic (DIF-FFT DA) models, with different adders such as Ripple carry adder (RCA), Carry-lookahead adder (CLA), and Sklansky prefix graph adder, are proposed in this paper. The three proposed models are synthesized using Cadence 6.1 EDA tools with a 45nm CMOS technology. Compared to the traditional method, it is observed that the area is improved by 53.11%, 53.35%, and 50.15%, power is improved by 42.31%, 42.52%, and 40.39%, and delay is improved by 45.26%, 45.42%, 41.80%, respectively.

Układy arytmetyki stochastycznej i ich implementacja w strukturach FPGA

Kawalec P.

Pomiary Automatyka Kontrola

2009

R. 55, nr 8

627-629

W artykule przedstawiono podstawowe układy arytmetyki stochastycznej zrealizowane w technice cyfrowej. W celu zapewnienia maksymalnej szybkości działania, syntezę układów arytmetyki stochastycznej przeprowadzono na elementach logicznych i przerzutnikach. Dla specjalizowanych układów sumatorów, subtraktorów, oraz multiplikatorów i układów potęgujących, wyznaczono dokładność przetwarzania. Przeprowadzono ich syntezę i implementację w układach FPGA, wyznaczając szybkość działania.

The paper presents fundamental circuits of stochastic arithmetic realized by means of digital technology. In order to ensure the maximum operational speed, synthesis of stochastic arithmetic circuits has been performed on logical elements and triggers. Specialized stochastic adders on NOT and NAND elements (Fig.1) as well as on multiplexers (Fig. 3) both without and with randomization of the input data (Fig. 2) have been designed for disjoint events in binary random sequences. Specification of stochastic adders has been conducted in VHDL language, and their verification - in functional simulation mode (Fig. 4). The accuracy of the stochastic adder operation has been determined, whereas synthesis and implementation of these systems in FPGA structure allowed for showing the speed of stochastic adder operation with the frequency of timing exceeding 100 MHz. Similar investigations have been carried out for specialized stochastic subtractors. For independent binary random sequences, stochastic multipliers and squaring circuits (Fig. 6) have been designed, having a structure particularly useful for realization within programmable logical FPGA structures.