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3 International Journal of Microelectronics and Computer Science

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Realization of logic integrated circuits in VeSTIC process - design, fabrication, and characterization

Domański Krzysztof, Głuszko Grzegorz, Sierakowski Andrzej, Tomaszewski Daniel, Szmigiel Dariusz

International Journal of Microelectronics and Computer Science

2018

Vol. 9, nr 3

123--132

A design and manufacturing of test structures for characterization of logic integrated circuits in a VeSTIC process developed in ITE, are described. Two variants of the VeSTIC processs have been described. A role and sources of the process variability have been discussed. The VeSFET I-V characteristics, the logic cell static characteristics, and waveforms of the 53-stage ring oscillator are presented. Basic parameters of the VeSFETs have been determined. The role of the process variability and of the parasitic elements introduced by the conservative circuit design, e.g. wide conductive lines connecting the devices in the circuits, have been discussed. Based on the inverter layout and on the process specification, the parasitic elements of the inverter equivalent circuit have been extracted. The inverter propagation times, the ring oscillator frequency, and their dependence on the supply bias have been determined.

Small-Signal Parameters of the VeSFET and Its Application in Analog Circuits

Kasprowicz D., Swacha B

International Journal of Microelectronics and Computer Science

2013

Vol. 4, nr 2

79--86

The Vertical Slit-based Field-Effect Transistor (VeSFET) is a novel junctionless device with two identical, independently controlled gates. The VeSFET, so far prototyped only as single-device test structures, has been considered in the literature exclusively as a component of digital systems. This article shows that the device’s properties make it attractive also for the analog designer. Some of the VeSFET’s analog-design related parameters are compared with those of the MOSFET of the corresponding technology node. Subsequently, a two-stage Miller operational transconductance amplifier (OTA) is proposed that makes use of the VeSFET’s two independently-controlled gates to drastically reduce the common-mode gain. An example application of the OTA in a current mirror is also presented.

Downscaling and short channel effects in twin gate junctionless vertical slit FETs

Barbut L, Jazaeri F, Bouvet D, Sallese J.-M.

International Journal of Microelectronics and Computer Science

2013

Vol. 4, nr 3

103--109

In this work, we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters, namely, the doping level in the channel, the minimum slit width, and the effective radius of the slit. This work could serve as a guideline for technology optimization, design and scaling of JL VeSFETs.