Wyniki wyszukiwania - BazTech

1

A power-balanced sequential element for the delay-based dual-rail precharge logic style

Bongiovanni S, Olivieri M, Scotti G., Trifiletti A.

International Journal of Microelectronics and Computer Science

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2013

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Vol. 4, nr 4

129--141

EN

Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits when a Power Analysis (PA) attack is mounted. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions. The purpose is to break the link between dynamic power and data statistics and preventing power analysis. In this work we present a novel implementation of a dynamic differential master-slave ﬂip-ﬂop which is compatible with the DDPL data encoding. Efforts were made in order to design a completely dynamic master-slave architecture which does not require a conversion of the signals from dynamic to static domain. Moreover we show that the area occupied is also reduced due to a compact differential layout. Simulations performed using a 65nm-CMOS process showed that the proposed circuit exhibits good performance in terms of NED (Normalized Energy Deviation) and CV (Coefﬁcient of Variation) of the current samples as required in transistor level countermeasures against power analysis, and it outperforms other previously published DPA-resistant ﬂip-ﬂops in the real case of unbalanced load conditions.

2

Using intelligent programming paradigm in CAD systems

Rogoza V.

Pomiary Automatyka Kontrola

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2009

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R. 55, nr 10

847-850

EN

The intelligent programming paradigm is considered as a concept that combines two basic properties of a sophisticated software, namely: adaptive tuning and evolutionary self-organization. Such properties can be realized at the algorithmic level using object-oriented programming languages.

PL

Paradygmat programowania inteligentnego jest rozpatrywany jako koncepcja, która łączy w sobie dwie zasadnicze własności skomplikowanego oprogramowania, mianowicie: adaptacyjne dostrajanie modeli i ich samoorganizacja ewolucyjna. W artykule pokazano, że omówione właściwości mogą być realizowane z wykorzystaniem specjalnych algorytmów syntezy modeli składników obiektów ulegających symulacji oraz paradygmatu programowania obiektowego.

3

Binary neural networks for N-queens problems and their VLSI implementations

Funabiki N., Kurokawa T., Ohta M.

Control and Cybernetics

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2002

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Vol. 31, no 2

271-296

EN

Combinatorial optimization problems compose an important class of matliematical problems that include a variety of practical applications, such as VLSI design automation, communication network design and control, job scheduling, games, and genome informatics. These problems usually have a large number of variables to be solved. For example, problems for VLSI design automation require several million variables. Besides, thieir computational complexity is often intractable due to NP-hardness. Neural networks have provided elegant solutions as approximation algorithms to these hard problems due to their natural parallelism and their affinity to hardware realization. Particularly, binary neural networks have great potential to conform to current digital VLSI design technology, because any state and parameter in binary neural networks are expressed in a discrete fashion. This paper presents our studies on binary neural networks to the N-queens problem, and the three different approaches to VLSI implementations focusing on the efficient realization of the synaptic connection networks. Reconfigurable devices such as CPLDs and FPGAs contribute the realization of a scalable architecture with the ultra high speed of computation. Based on the proposed architecture, more than several thousands of binary neurons can be realized on one FPGA chip.