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1

Technical solutions and SPICE modelling of optical sensors

Wójcik Waldemar

Przegląd Elektrotechniczny

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2020

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R. 96, nr 10

102--105

EN

Paper represents the technical and circuit solutions of optoelectronic sensors designing. The noise in information signal such as a parasitic effect of external (non-informative) optical radiation and electromagnetic interference could be decreased using hardware and software "GIRATO" package. The main results of this implementation by using SPICE simulation was carried out in our paper.

PL

Artykuł przedstawia rozwiązania techniczne i układowe w zakresie projektowania czujników optoelektronicznych. Szumy w sygnale informacyjnym, takie jak pasożytniczy efekt zewnętrznego (nieinformacyjnego) promieniowania optycznego i zakłóceń elektromagnetycznych, mogą być zmniejszone za pomocą pakietu sprzętowego i programowego "GIRATO". Główne wyniki tej realizacji z wykorzystaniem symulacji SPICE zostały przedstawione w naszym artykule.

2

Analysis of a Simple Method of CMOS IC Design for Yield Optimization

Tomaszewski D., Yakupov M.

International Journal of Microelectronics and Computer Science

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2012

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Vol. 3, nr 3

81-87

EN

A simple approach for CMOS integrated circuit (IC) design taking into account a process variability and oriented towards optimization of a parametric yield has been presented. Its concept is based on cumulative distribution functions of random variables representing IC performances subject to process variations. In the method it has been assumed that CMOS process statistical data are expressed in terms of so-called process parameter distributions. Thus the design centering is done via layout parameter tuning. The approach relies on maximizing the probability that random variables corresponding to IC performances remain within the performance boundaries. Also, a methodology for statistical characterization of CMOS process has been briefly described. Finally, the method operation has been illustrated using analytical and SPICE models of CMOS inverter, operational amplifier and ring oscillator.

3

Modelowanie obwodowe transformatora piezoelektrycznego w warunkach podwyższonych napięć i temperatur

Tomalczyk K.

Pomiary Automatyka Kontrola

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2011

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R. 57, nr 10

1206-1209

PL

Artykuł dotyczy modelowania obwodowego transformatorów piezoelektrycznych (PT) przy napięciach i temperaturach zbliżonych do panujących w rzeczywistych warunkach ich pracy. Typowe metody modelowania PT wykorzystują obwód zastępczy o stałych parametrach wyznaczanych przy niskim napięciu i temperaturze. W artykule potwierdzony został wpływ zarówno amplitudy napięcia wejściowego, jak i temperatury, na charakterystyki przejściowe PT. Aby uwzględnić stwierdzone zależności przy modelowaniu obwodowym PT, opracowana została metoda korekcji parametrów modelu PT uwzględniająca zmiany ich wartości w funkcji temperatury i napięcia wejściowego. Metoda ta pozwala uzyskać dużo lepszą zgodność wyników symulacji obwodowych z wynikami pomiarowymi w warunkach podwyższonych napięć i temperatur.

EN

The paper refers to circuit modeling of piezoelectric transformers (PTs) operating under elevated voltage and temperature conditions. A PT is a resonant mechanical converter of electrical energy. Its characteristics (Fig. 1) are modeled by an equivalent circuit (Fig. 2) whose parameters are typically determined under low-voltage and low-temperature conditions and remain constant regardless of the model application. This approach is possibly erroneous due to the known temperature dependency and nonlinearities of piezoelectric materials. The temperature- and voltage-dependent variation of PT model parameters (Fig. 3) was determined by means of time domain measurements, which contrary to the widely used impedance analysis, allows high input voltages. A method for correction of the model parameters was established. Furthermore, the PT transfer characteristics were measured (Figs. 4 and 5) and compared to simulation results with and without the parameter correction (Fig. 6), showing considerable improvement in modeling accuracy with the new method applied.

4

Comparison of Various SC FIR Filter Structures on the Basis of their CMOS Realization and Simulation in the PSPICE Program

Dąbrowski A., Długosz R.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2001

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vol. 49, nr 1

59-79

EN

In this paper switched-capacitor finite impulse response (SC FIR) filter structures are considered and developed. Their performance (i.e., general features, quality of operation, influence of parasitic capacitance, the chip area requirements, etc.) are analyzed and compared for various possible SC FIR structures. The comparisons are not only based on the method for the chip area estimation, proposed by authors in [1], but also on the precise chip area determination by means of the simulation of the considered circuits using the PSPICE program and by means of their design in the [formula] CMOS technology. Special attention is paid in this paper to the decomposition of FIR delay-line filter structures into second order sections (and possibly into a single first order section). The importance of such decomposition for the reduction of the required chip area occurred to be evident during the design process.