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1

RNS/TCS converter design using high-level synthesis in FPGA

Smyk R., Czyżak M.

Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej

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2017

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Nr 57

121--126

EN

An experimental high-level synthesis (HLS) of the residue number system (RNS) to two’s-complement system (TCS) converter in the Vivado Xilinx FPGA environment is shown. The assumed approach makes use of the Chinese Remainder Theorem I (CRT I). The HLS simplifies and accelerates the design and implementation process, moreover the HLS synthesized architecture requires less hardware by about 20% but the operational frequency is smaller by 30% than that for the VHDL designed converter.

PL

W pracy przedstawiono eksperymentalną wysokopoziomową syntezę w FPGA konwertera L systemu resztowego do systemu reprezentacji z uzupełnieniem do 2 (U2). W zastosowanym podejściu wykorzystano algorytm konwersji na bazie chińskiego twierdzenia o resztach (CRT 1), Zauważono, że synteza wysokopoziomowa ułatwia proces projektowania oraz zauważalnie skraca czas testowania układu. Zaprojektowana architektura konwertera przy wykorzystaniu syntezy wysokopoziomowej pochłania o około 20% zasobów układu FPGA mniej niż dla konwertera zaprojektowanego przy użyciu języka VHDL, jednak maksymalna częstotliwość pracy jest niższa o około 30%.

2

Scaling of numbers in residue arithmetic with the flexible selection of scaling factor

Ulman Z., Czyżak M., Smyk R.

Poznan University of Technology Academic Journals. Electrical Engineering

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2013

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No. 76

175--179

EN

A scaling technique of numbers in residue arithmetic with the flexible selection of the scaling factor is presented. The required scaling factor can be selected from the set of moduli products of the Residue Number System (RNS) base. By permutation of moduli of the number system base it is possible to create many auxiliary Mixed-Radix Systems (MRS). They serve as the intermediate systems in the scaling process. All MRS's are associated with the given RNS with respect to the base, but they have different sets of weights. For the scaling factor value resulting from the requirements of the given signal processing algorithm, the suitable MRS can be chosen that allows to obtain the scaling result in most simple manner.

3

Residue number system (RNS)

Sharoun A. O.

Poznan University of Technology Academic Journals. Electrical Engineering

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2013

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No. 76

265--270

EN

In the residue number system, a set of moduli which are independent of each other is given. An integer is represented by the residue of each modulus and the arithmetic operations are based on the residues individually. The arithmetic operations based on residue number system can be performed on various moduli independently to avoid the carry in addition, subtraction and multiplication, which is usually time consuming. However, the comparison and division are more complicated and the fraction number computation is immatured. Due to this, a residue number system is not yet popular in general-purpose computers, though it is extremely useful for digital-signal-processing applications. This thesis deals with the design, simulation and microcontroller implementation of some (residue number system based) building blocks for applications in the field of digital signal processing. The building blocks which have been studied are binary to residue converter, residue to binary converter, residue adder and residue multiplier.

4

Pipelined division of signed numbers with the use of residue arithmetic for small number range with the programmable gate array

Smyk R., Ulman Z., Czyżak M.

Poznan University of Technology Academic Journals. Electrical Engineering

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2013

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No. 76

117--126

EN

In this work an architecture of the pipelined signed residue divider for the small number range is presented. Its operation is based on reciprocal calculation and multiplication by the dividend. The divisor in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to limit the look-up table address an algoritm based on segmentation of the divisor into two segments is used. The approximate reciprocal transformed to residue representation with the proper sign is stored in look-up tables. During operation it is multiplied by the dividend in the residue form and subsequently scaled. The pipelined realization of the divider in the FPGA environment is also shown.

5

Określanie parzystości liczb w resztowym systemie liczbowym z wykorzystaniem konwersji do systemu z mieszanymi podstawami

Plebanek M.

Poznan University of Technology Academic Journals. Electrical Engineering

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2013

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No. 76

127--134

PL

W artykule przedstawiono metodę konwersji liczb z systemu resztowego do systemu z mieszanymi podstawami. Następnie zaprezentowano dwie metody konwersji liczb z systemu z mieszanymi podstawami do systemu dziesiętnego, oraz metodę określania parzystości i porównywania liczb zapisanych w systemie z mieszanymi podstawami.

EN

Conversion method between RNS and MRS numeric systems was presented in article. Also two methods of conversion from MRS to decimal system and algorithms of parity detection in MRS are shown. At last two methods of comparison of numbers in MRS are presented.

6

Scaling of signed residue numbers with mixed-radix conversion in FPGA with extended scaling factor selection

Smyk R., Czyżak M., Ulman Z.

Computer Applications in Electrical Engineering

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2013

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Vol. 11

465--477

EN

A scaling technique of signed residue numbers in FPGA is proposed. The technique is based on conversion of residue numbers to the Mixed-Radix System (MRS). The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of MRS terms, the subsequent generation of residue representations of scaled terms, binary addition of these representations and generation of residues for all moduli. The sign of the residue number is detected by using the most significant digit of the MRS representation. Basic blocks of the scaler are realized in the form of modified two-operand modulo adders with included additional multiply and modulo reduction operations. An exemplary pipelined realization of the scaler in the Xilinx FPGA environment is shown. The design is based on Look-Up Tables (LUT)(2,sup>6 x 1) that simulate small RAMs which serve as main components for the look-up realization. Also a method is shown that allows for flexible selection of scaling factors from a set of moduli products of the RNS base. This is made by forming auxiliary MRSs by permutation of moduli of the base. All formed MRSs are associated with the given RNS with respect to the base but each MRS has different set of weights. Thus for the required scaling factor, the suitable MRS can be chosen that provides for the scaling error smaller than 1.

7

FPGA implementation of reverse residue conversion based on the new Chinese Remainder Theorem II- Part II: experimental results

Ulman Z., Czyżak M., Smyk R.

Poznan University of Technology Academic Journals. Electrical Engineering

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2012

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No. 71

139--147

EN

This work describes a hardware realization of the converter of numbers from the Residue Number System (RNS) to the binary system. The converter is based on the new form of the Chinese Remainder Theorem (CRT) termed the New CRT II. The theoretical aspects of conversion by this method have been described in Part I. The implementation of the converter has been carried out in the Xilinx FPGA environment. The general architecture of the system is shown, also the realizations of the selected blocks of the converter are described. The hardware amount and attainable pipelining rate are given. The converter has been realized for the RNS base composed of eight 5-bit moduli that gives the dynamic range of about 37 bits.

8

FPGA implementation of reverse residue conversion based on the new Chinese Remainder Theorem II- Part I

Ulman Z., Czyżak M., Smyk R.

Poznan University of Technology Academic Journals. Electrical Engineering

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2012

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No. 71

133--138

EN

This work describes a derivation and an implementation of the algorithm of conversion from the Residue Number System (RNS) to the binary system based on the new form of the Chinese Remainder Theorem (CRT) termed the New CRT II. The new form of the CRT does not require the modulo M operation, where M is the residue number system range, but a certain number of multipliers is needed. Because in the FPGA environments the multipliers or the special DSP blocks are available, so they can be used in the converter realization. The main aim of the work is to examine experimentally the needed hardware amount and the influence of the multipliers on the maximum pipelining frequency. In Part I the derivation of the conversion algorithm is described. In Part II the hardware implementation of the converter in the FPGA technology is shown.

9

Arytmetyka resztowa w szyfrowaniu RSA

Jabłoński A.

Przegląd Elektrotechniczny

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2010

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R. 86, nr 9

145-148

PL

W artykule przedstawiona została metoda poprawy efektywności szyfrowania RSA. Proponowane rozwiązanie korzysta z resztowej reprezentacji liczb (ang. Residue Number System, RNS) oraz konwersji z systemu resztowego do stałobazowego zaproponowanej przez Wang-a. RNS prowadzi do redukcji rozmiaru czynników oraz wprowadzenia zrównoleglenia przetwarzania na poziomie algorytmu. Natomiast Małe Twierdzenie Fermata zostało wykorzystane do redukcji wykładnika w schemacie RSA.

EN

This article presents efficiency improvement method for the RSA coding. Proposed solution uses Residue Number System as well as conversion proposed by Wang’a. The Residue Number System (RNS) leads to reduction of size of factors as well as the induction the parallel processing on level of algorithm. In proposed solution the Small Fermat Theory and Wang conversion was used to reduction of exponent in RSA schema.