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EN
The paper presents the hardware implementation of the elementary computations, termed the butterflies, of the convolution realized with a use of the Polynomial Residue Number System (PRNS). The computations are performed with the use of the diminished-1 number representation. The synthesis of the butterflies in the Xilinx ISE environment with Virtex 4 model is described, the hardware amount and pipelining rate are also given.
EN
This paper presents the study of fast discrete convolution calculation with use of the Polynomial Residue Number System (PRNS). Convolution can be based the algorithm similar to polynomial multiplication. The residue arithmetic allows for fast realization of multiplication and addition, which are the most important arithmetic operations in the implementation of convolution. The practical aspects of hardware realization of PRNS convolution in Xilinx FPGA are also presented.
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