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1 International Journal of Electronics and Telecommunications

1 2025

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Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic)

Satyanarayana D., Chennakesavulu M., Sulthana N. Fouzia, Upendra K., Sashidhar D., Reddy K.Ramachandra, Vikranth N.Naga Sai, Devendra V.

International Journal of Electronics and Telecommunications

2025

Vol. 71, No. 2

483-488

The demand for low-power, high-speed, and area efficient digital circuits has driven the exploration of alternative logic families such as Pass Transistor Logic (PTL). The design of a multiplier circuit that leverages the inherent advantages of PTL to achieve significant improvements in power consumption, operational speed and silicon area usage. The proposed multiplier using PTL-based logic gates to generate partial products, followed by a reduction tree and a final addition stage, all optimized for performance and efficiency. Key design challenges, such as voltage degradation and level restoration inherent in PTL circuits, is addressed through carefully designed voltage restoration techniques and custom PTL cells. The architecture is compared against conventional CMOS-based multipliers to demonstrate its superiority in terms of power efficiency and speed. All the circuits are simulated using ECAD tools to analyze the power, delay, area and Power-Delay-Product (PDP) of the multiplier to highlight a substantial reduction in power consumption and a faster operation, making the PTL-based multiplier an ideal circuit for high-performance and low-power applications in modern digital systems. The proposed work contributes to the field of low-power digital design by showcasing the potential of PTL in creating multipliers which are not only efficient but also scalable for future technology nodes.