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1

Reducing the number of LUTs for Mealy FSMs with state transformation

Barkalov Alexander, Titarenko Larysa, Mielcarek Kamil

International Journal of Applied Mathematics and Computer Science

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2024

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Vol. 34, no. 1

167--178

EN

In many digital systems, various sequential blocks are used. This paper is devoted to the case where the model of a Mealy finite state machine (FSM) represents the behaviour of a sequential block. The chip area occupied by an FSM circuit is one of the most important characteristics used in logic synthesis. In this paper, a method is proposed which aims at reducing LUT counts for FPGA-based Mealy FSMs with transformation of state codes into FSM outputs. This is done using the combined state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed method leads to LUT-based Mealy FSM circuits having exactly three levels of logic blocks. Under certain conditions, each function for any logic level is represented by a circuit including a single LUT. The proposed approach is illustrated with an example of synthesis. The results of experiments conducted using standard benchmarks show that the proposed method produces LUT-based FSM circuits with significantly smaller LUT counts than is the case for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of binary codes into extended state codes). The LUT count is decreased by an average of 17.96 to 91.8%. Moreover, if some conditions are met, the decrease in the LUT count is accompanied with a slight improvement in the operating frequency compared with circuits based on extended state codes. The advantages of the proposed method multiply with increasing the numbers of FSM inputs and states.

2

Zastosowanie zasad projektowania uniwersalnego do ulepszenia stron internetowych wybranej uczelni wyższej

Kamiński Tomasz, Kapica Paweł, Dzieńkowski Mariusz

Journal of Computer Sciences Institute

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2022

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Vol. 25

401--408

PL

Celem pracy była analiza strony internetowej wybranej uczelni pod względem użyteczności i dostępności interfejsów użytkownika ze szczególnym uwzględnieniem wytycznych zawartych w standardzie WCAG (ang. Web Content Accessibility Guidelines). Po uwzględnieniu wszystkich wytycznych powstała ulepszona prototypowa wersja witryny, która została pozbawiona zdiagnozowanych błędów i niezgodności. Obie witryny zostały przebadane trzema metodami: metodą kwestionariuszową za pomocą listy kontrolnej LUT, z wykorzystaniem techniki okulograficznej oraz automatycznego narzędzia - wtyczki WAVE dołączonej do przeglądarki internetowej. W badaniach ankietowych i okulograficznych wzięło udział 20 uczestników. Dane pozyskane zbadań wykonanych trzema metodamizostały poddane analizie ilościowej. Natomiast wyniki badań eyetrackingowych zostały dodatkowo poddane analizie jakościowej (mapy cieplne, ścieżki skanowania).Wyniki przeprowadzonych analiz jednoznacznie pokazują, że prototypowa witryna przygotowana przez autorów pracy zgodnie z zasadami projektowania uniwersalnegowyraźnie lepiej wypada pod względem użyteczności i dostępności niż witryna wybranej uczelni.

EN

The purpose of the study was to analyze the website of a selected university in terms of usability and accessibility of user interfaces with particular attention to the guidelines of the Web Content Accessibility Guidelines (WCAG) standard. After taking into account all the guidelines, an improved version of the site was created that was free of the diagnosed errors and incompatibilities. Both sites were surveyed using the questionnaire method with the LUT checklist. A survey was also conducted using an eyetracker. Twenty participants took part in this study. The third method of evaluation was to analyze the sites using an automated tool - the WAVE plugin attached to a web browser. The data obtained from the research experiment were analyzed qualitatively and quantitatively. In case of the survey and the WAVE tool, only quantitative analysis was carried out. The results of the analyses carried out using the three methods show unequivocally that the author's website prepared by the authors is clearly better in terms of usability and accessibility than the website of the selected university.

3

Improving the LUT count for Mealy FSMs with transformation of output collections

Barkalov Alexander, Titarenko Larysa, Mazurkiewicz Małgorzata

International Journal of Applied Mathematics and Computer Science

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2022

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Vol. 32, no. 3

479--494

EN

A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state machines (FSMs) with transformation of collections of outputs into state codes. The reduction is achieved due to the use of two-component state codes. Such an approach allows reducing the number of state variables compared with FSMs based on extended codes. There are exactly three levels of LUTs in the resulting FSM circuit. Each partial function is represented by a single-LUT circuit. The proposed method is illustrated with an example of synthesis. The experiments were conducted using standard benchmarks. They show that the proposed method produces FSM circuits with significantly smaller LUT counts compared with those produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of output collection codes into extended state codes). The LUT count is decreased by, on average, from 9.86% to 59.64%. The improvement of the LUT count is accompanied by a slightly improved performance. The maximum operating frequency is increased, on average, from 2.74% to 12.93%. The advantages of the proposed method become more pronounced with increasing values of FSM inputs and state variables.

4

Evaluation of remote learning at technical universities during a pandemic – the perspectives for the future

Gaweł Dariusz

Teka Komisji Architektury, Urbanistyki i Studiów Krajobrazowych

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2021

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T. 17, nr 4

57--63

EN

This article is a summary of a research conducted in the conditions of remote teaching of undergraduate and postgraduate students at technical university. The research referred to the effectiveness and perspectives of web-based education (under the conditions of lockdown) during the COVID-19 pandemic. The aim of the research was to assess the quality of courses and involvement of students in the learning process. One year after the introduction of this form of learning at universities, certain phenomena can be observed, which allow us to draw the first conclusions. In the final part of the study, the author discusses the possibility to continue and use this form of education once the pandemic has passed. The familiarisation and adaptation of students to this specific character of courses in the conditions of a pandemic was a stimulus to interpret this state as a long-term form of education that can change future ways and forms of teaching at universities, including technical universities

5

Improving LUT count of FPGA-based sequential blocks

Barkalov Alexander, Titarenko Larysa, Mazurkiewicz Małgorzata, Krzywicki Kazimierz

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2021

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Vol. 69, nr 2

art. no. e136728

EN

Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and consumed energy. The paper proposes a novel technology-dependant design method targeting LUT-based Mealy FSMs. It belongs to the group of structural decomposition methods. The method is based on encoding the product terms of Boolean functions representing the FSM circuit. To diminish the number of LUTs, a partition of the set of internal states is constructed. It leads to three-level logic circuits of Mealy FSMs. Each function from the first level requires only a single LUT to be implemented. The method of constructing the partition with the minimum amount of classes is proposed. There is given an example of FSM synthesis with the proposed method. The experiments with standard benchmarks were conducted. They show that the proposed method can improve such FSM characteristics as the number of used LUTs. This improvement is accompanied by a decrease in performance. A positive side effect of the proposed method is a reduction in power consumption compared with FSMs obtained with other design methods.

6

Improving characteristics of LUT-based Mealy FSMs

Barkalov Alexander, Titarenko Larysa, Mielcarek Kamil

International Journal of Applied Mathematics and Computer Science

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2020

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Vol. 30, no. 4

745--759

EN

Practically, any digital system includes sequential blocks represented using a model of finite state machine (FSM). It is very important to improve such FSM characteristics as the number of logic elements used, operating frequency and consumed energy. The paper proposes a novel technology-dependent design method targeting a decrease in the number of look-up table (LUT) elements and their levels in logic circuits of FPGA-based Mealy FSMs. It produces FSM circuits having three levels of logic blocks. Also, it produces circuits with regular systems of interconnections between the levels of logic. The method is based on dividing the set of internal states into two subsets. Each subset corresponds to a unique part of an FSM circuit. Only a single LUT is required for implementing each function generated by the first part of the circuit. The second part is represented by a multi-level circuit. The proposed method belongs to the group of two-fold state assignment methods. Each internal state is encoded as an element of the set of states and as an element of some of its subsets. A binary state assignment is used for states corresponding to the first part of the FSM circuit. The one-hot assignment is used for states corresponding to the second part. An example of FSM synthesis with the proposed method is shown. The experiments with standard benchmarks are conducted to analyze the efficiency of the proposed method. The results of experiments show that the proposed approach leads to diminishing the number of LUTs in the circuits of rather complex Mealy FSMs having more than 15 internal states. The positive property of this method is a reduction in energy consumption (without any overhead cost) and an increase in operating frequency compared with other investigated methods.

7

Evaluation of Selected Timing Parameters of FPGA Device

Sondej D., Szymanowski R., Szplet R.

Measurement Automation Monitoring

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2018

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Vol. 64, No. 1

23--25

EN

We present a method and results of measurements of FPGA (Field Programmable Gate Array) selected timing parameters crucial in many timing sensitive applications such as precise time and frequency metrology. Two main parameters, i.e. the delay and its jitter, were evaluated for look-up-tables (delay 740 ps/jitter 1.33 ps), IO buffers (na/0.45 ps) and carry-chain multiplexers (28ps/0.153 ps) integrated in a programmable device Spartan-6 (Xilinx) which is one of most popular FPGA chips on the market now. Measurements were performed with the use of fast real-time sampling oscilloscope.

8

Hardware reduction for LUT-based mealy FSMs

Barkalov A., Titarenko L., Mielcarek K.

International Journal of Applied Mathematics and Computer Science

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2018

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Vol. 28, no. 3

595--607

EN

A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each state has two codes. It diminishes the number of arguments in input memory functions. An example of synthesis is given, along with results of investigations. The method targets rather complex FSMs, having more than 15 states.

9

Functional decomposition of combinational logic circuits with PKmin

Michalski T., Kokosiński Z.

Czasopismo Techniczne. Elektrotechnika

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2016

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Y. 113, iss. 2-E

191--202

EN

In this paper, an application of the PKmin program for functional decomposition of multiinput multi-output combinational circuits is presented. The main focus is on balanced multilevel decomposition of logic circuits into minimal number of blocks, such as LUTs in FPGAs. Reduction of the input redundancy is available. Decomposition schemes include parallel, joint/disjoint serial and a mixed one. The decomposition with PKmin can be automated by means of a heuristic algorithm or can be supervised by the designer. A distinctive feature of PKmin is the visualization of the design steps and the final layout of blocks and their interconnections. PKmin is compared in an example with the program DEMAIN.

PL

W artykule przedstawiono zastosowanie programu PKmin do dekompozycji funkcjonalnej wielowyjściowych układów kombinacyjnych, a w szczególności do wielopoziomowej dekompozycji układów na minimalną liczbę bloków funkcjonalnych, takich jak komórki LUT w makrokomórkach FPGA. Możliwa jest wstępna redukcja wejść, a następnie dekompozycje: równoległa, szeregowa łączna i rozłączna oraz mieszana. Proces dekompozycji może być zautomatyzowany lub nadzorowany przez projektanta w trybie interaktywnym. Wyróżnikiem PKmin jest wizualizacja procesu projektowania. Końcowy schemat układu zawiera bloki składowe LUT oraz ich połączenia. Program PKmin został porównany na przykładzie z programem DEMAIN.

10

Kodowanie klas POLC w mikroprogramowanych układach sterujących

Barkalov A., Titarenko L., Bieganowski J.

Pomiary Automatyka Kontrola

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2012

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R. 58, nr 1

97-100

PL

W artykule przedstawiono rezultaty syntezy sześciu struktur układów mikroprogramowanych (CMCU), które wykorzystują koncepcję podziału zbioru łańcuchów operacyjnych na klasy łańcuchów pseudorównoważnych (POLC). Przedstawione w pracy struktury układów mikroprogramowanych są przeznaczone przede wszystkim do zastosowania w układach FPGA. Część kombinacyjna układu mikroprogramowanego jest realizowana z użyciem tablic LUT, natomiast pamięć sterująca jest implementowana z użyciem osadzonych bloków pamięci. Badania przeprowadzono dla czterech popularnych kodowań stanów: kodowania binarnego, kodowania one-hot, kodowania Gray'a oraz kodowania Johnson'a.

EN

The paper presents new synthesis results of six structures of a compositional microprogram control unit (CMCU) targeted mainly at FGPAs. The structure of CMCU consist of two main parts: a control memory and an addressing circuit. The control memory stores microinstructions which are sent to the data path. The addressing circuit is responsible for selecting a microinstruction from the control memory. The addressing part of the CMCU is implemented using LUT tables, while the control memory is implemented using embedded memory blocks (EMB). Partitioning the set of operational linear chains (OLC) into pseudoeqivalent classes of chains (POLC) is used in all structures to reduce the size of the CMCU addressing part. The codes of POLCs are stored in the control memory by extending the microinstruction format or by inserting additional control microinstructions (Figs. 2, 3 and 4). The CMCU structures were tested using linear graph-schemes of the algorithm (see Tab. 1). The synthesis was made in Xilinx ISE and Altera Quartus for FPGA and CPLD devices. The synthesis results (Figs. 5 and 6) show that the size of the combinational part for the tested CMCU structures can be reduced by 20% to 50% depending on the CMCU structure (when compared to the base structure - average results). The results also show that the natural binary encoding and Gray's encoding are best for POLC classes. Both encodings give the smallest size of the addressing part and require less control memory space.

11

O implementacjach sprzętowych transformacji falkowej

Rakowski W.

Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne

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2003

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nr 2-3

77-81

PL

Zawarto krótkie wprowadzenie do reprezentacji falkowej sygnałów. Opisano układ filtrów cyfrowych umożliwiający dekompozycję i rekonstrukcję falkową sygnałów. Podano algorytmy i schematy implementacji filtracji cyfrowej w szeregowej arytmetyce rozproszonej. Omówiono sposób dekompozycji tablic LUT oraz realizację decymacji sygnału i implementację filtrów symetrycznych.

EN

Paper contains a short introduction to the wavelet representation of signals and the two-channel filter bank allowing the wavelet decomposition and reconstruction. Efficient distributed arithmetic architectures of digital filtering suitable for FPGA implementation was derived and illustrated. A partitioning algorithm permitting to avoid a large lookup tables was described. Circuit structures implementing signal decimation and making use of filter symmetry was shown.

12

Potokowe obliczenia argumentu funkcji przejścia dla warstwy neuronów z wykorzystaniem FPGA

Rybarczyk A., Nowakowski B.

Elektronizacja : podzespoły i zastosowania elektroniki

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2003

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Vol. 23, nr 10

25-27

PL

Przedstawiono potokowo-równoległą metodę obliczeń argumentów funkcji przejścia dla warstw neuronowych, zoptymalizowaną pod kątem wykorzystania w matrycach programowalnych FPGA. Opisano konkretne rozwiązanie problemu przyspieszenia obliczeń w sieci neuronowej implementowanej na układach cyfrowych. Wykorzystanie tej metody umożliwia wielokrotne przyspieszenie obliczeń w porównaniu z tradycyjną metodą obliczeń szeregowych.

EN

The paper presents the realisation of an artifical neural network (ANN), which uses parallel-pipeline method of calculating the arguments of the transition function for neuron layers. The paper also evaluated the performance and the speed of such a network basing on optimisation for programmable FPGA arrays. The paper describes a way of accelerating calculations in a digitally implemented neural network. The calculation time is about ten times lower compared to the traditional sequential processing.