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Content available remote On Random Number Generation for Kernel Applications
EN
An operating system kernel uses cryptographically secure pseudorandom number generator (CSPRNG) for creating address space layout randomization (ASLR) offsets to protect memory addresses of processes from exploitation, storing users' passwords securely and creating cryptographic keys. However, at present, popular kernel CSPRNGs such as Yarrow, Fortuna and /dev/(u)random which are used by MacOS/iOS/FreeBSD, Windows and Linux/Android kernels respectively lack the very crucial property of non-reproducibility of their generated bitstreams which is used to nullify the scope of predicting the bitstream. This paper proposes a CSPRNG called Cryptographically Secure Pseudorandom Number Generator for Kernel Applications (KCS-PRNG) which generates non-reproducible bitstreams. The proposed KCS-PRNG presents an efficient design uniquely configured with two new non-standard and verified elliptic curves and clock-controlled Linear Feedback Shift Registers (LFSRs) and a novel method to consistently generate non-reproducible random bitstreams of arbitrary lengths. The generated bitstreams are statistically indistinguishable from true random bitstreams and provably secure, resilient to important attacks, exhibits backward and forward secrecy, exhibits exponential linear complexity, large period and huge key space.
EN
This paper proposes an attack on a recently proposed cryptosystem using bilateral-diffusion algorithm with dynamical compound chaos. The original image encryption scheme employed a compound chaotic function and (linear feedback shift register) LFSR. Experimental results of the studied scheme showed that it is strong enough to resist against different attacks. The method used in the cryptosystem under study, presents weakness and a chosen plaintext attack can be done to recover the plain image without any knowledge of the key value. Only one pair of (plaintext/cipher text) is needed to totally break the cryptosystem.
PL
W artykule zaproponowano atak na kryptosystem wykorzystujący algorytm bilateral-diffusion z dynamiczna składową chaosu. Pokazano że jest możliwe wystarczająco mocny opór przeciwko różnym atakom. Jest więc możliwe odzyskanie obrazu.
EN
A new method of noise generation based on software implementation of a 7-bit LFSR based on a common polynomial PRBS7 using microcontrollers equipped with internal ADCs and DACs and a microcontroller noise generator structure are proposed in the paper. Two software applications implementing the method: written in ANSI C and based on the LUT technique and written in AVR Assembler are also proposed. In the method the ADC results are used to reseed the LFSR after its each full work cycle, what improves randomness of generated data, which results in a greater similarity of the generated random signal to white noise, what was confirmed by the results of experimental research. The noise generator uses only the internal devices of the microcontroller, hence the proposed solution does not introduce hardware redundancy to the system.
EN
In this article the statistical tests results of the pseudo random sequences generated by the Linear Feedback Shift Registers (LFSR) generators were described. LFSR generators' structures were shown and used statistical tests were described. The generator output sequence was analyzed in the NIST Statistical Test Suite STS 2.1.1. Interpretation of data obtained from the NIST STS 2.1.1 and the analysis' results of the pseudo random test sequences were discussed.
PL
W pracy przedstawiono nową metodę wykrywania przesłuchów w połączeniach. Testowaniu poddaje się tylko te połączenia FPGA, które będą wykorzystywane przez docelową aplikację. Zaproponowana struktura testera wbudowanego (BIST) wykorzystuje rejestr pierścieniowy 3n R LFSR, który w swojej części odpowiedzialnej za generowanie par testowych ma podwojoną liczbę przerzutników. Do testowanej sieci n połączeń jest podłączony tylko co drugi przerzutnik. Taka struktura generuje wszystkie pary niezbędne do pobudzenia przesłuchów co jest niemożliwe w klasycznej strukturze R-LFSR. Eksperymenty potwierdziły skuteczność testera BIST w pobudzaniu określonych przesłuchów.
EN
A new method of detection of crosstalk faults is presented in the paper. An interconnect network employed by a target application is a sole subject of the test. The detection of crosstalk fault requires stimulation of the interconnect network under test (INUT) with two consecutive test patterns. The test patterns have to be applied to inputs of the INUT at a nominal clock frequency. So using the Built In Self Test (BIST) is a must. The proposed BIST structure is based on a ring register called 3n R LFSR (Fig.1). In contrast to a typical ring register, the 3n R LFSR contains a double number 2n of flip flops in its part that is responsible for two test pattern generation. The n lines of the INUT are fed from the outputs of every second flip flop of that part of the register. Such structure of the BIST is capable of generating all two test patterns that are required to stimulate crosstalk faults in the INUT, which is impossible in the case of a classical R LFSR. At the beginning of a test session the 3n-R-LFSR is seeded with a chosen value. After g clock cycles the final state (signature) is read. In more complex cases crosstalk can be observed only if a number k of lines being aggressors change their state simultaneously. The experiments proved that for k << n it is possible to find the initial seed being the beginning of a test sequence, that stimulate all required crosstalks. The length of the test sequence and simulation time ? necessary for finding initial seed is acceptable (Tab. 3).
PL
W pracy zasygnalizowano konieczność testowania przesłuchów metodą test-per-clock przy pełnej szybkości zegara w sieciach długich połączeń między modułami w jednoukładowych systemach typu SoC. Do generacji testów zaproponowano rejestr LFSR (ang. Linear Feedback Shift Register) z wielomianem pierwotnym oraz z podwojoną liczbą przerzutników, w którym tylko co drugi przerzutnik jest podłączony do testowanej sieci połączeń. Przeprowadzono eksperymenty symulacyjne sprawdzające skuteczność ich wykorzystania do testowania przesłuchów objawiających się albo chwilowym zakłóceniem (szpilką) albo opóźnieniem zbocza.
EN
The paper is devoted to a test-per-clock method of an at-speed testing of crosstalk faults in long interconnects between cores in a System-on-a-Chip. A LFSR composed of 2n flip-flops and implementing primitive polynomial was used as a Test Pattern Generator (TPG) for an interconnect network comprised of n nets. In our approach every second output of the LFSR is connected to the Interconnect Network Under Test. Simulation-based experiments were carried out to verify effectiveness of vector sequences produced by the proposed TPG in detection of crosstalk faults provoked at victim net by simultaneous occurrence of rising (falling) edges 01(10) at k aggressor lines. Crosstalk faults causing occurrence of a positive (negative) glitch at a victim line having constant value 00(11) as well as ones that lead to delaying an edge with an opposite direction 10(01) at a victim line were taken into consideration. The experimental results show that for n ? {8,12,16,20,24,28,32} and k << n all above-mentioned crosstalk faults can be detected by a test sequence having an acceptable length.
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