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Porting of finite element integration algorithm to Xeon Phi coprocessor-based HPC architectures

Krużel Filip, Banaś Krzysztof, Iacomo Mauro

Computer Assisted Methods in Engineering and Science

2023

Vol. 30, no. 4

427--459

In the present article, we describe the implementation of the finite element numerical integration algorithm for the Xeon Phi coprocessor. The coprocessor was an extension of the many-core specialized unit for calculations, and its performance was comparable with the corresponding GPUs. Its main advantages were the built-in 512-bit vector registers and the ease of transferring existing codes from traditional x86 architectures. In the article, we move the code developed for a standard CPU to the coprocessor. We compareits performance with our OpenCL implementation of the numerical integration algorithm, previously developed for GPUs. The GPU code is tuned to fit into a coprocessor by ourauto-tuning mechanism. Tests included two types of tasks to solve, using two types of approximation and two types of elements. The obtained timing results allow comparing the performance of highly optimized CPU and GPU codes with a Xeon Phi coprocessor performance. This article answers whether such massively parallel architectures perform better using the CPU or GPU programming method. Furthermore, we have compared the Xeon Phi architecture and the latest available Intel’s i9 13900K CPU when writing this article. This comparison determines if the old Xeon Phi architecture remains competitive in today’s computing landscape. Our findings provide valuable insights for selectingthe most suitable hardware for numerical computations and the appropriate algorithmic design.

Feasibility of FPGA to HPC computation migration of plasma impurities diagnostic algorithms

Linczuk P., Krawczyk R. D., Zabolotny W., Wojenski A., Kolasinski P., Pozniak K. T., Kasprowicz G., Chernyshova M., Czarski T.

International Journal of Electronics and Telecommunications

2017

Vol. 63, No. 3

323--328

We present a feasibility study of fast events parameters estimation algorithms regarding their execution time. It is the first stage of procedure used on data gathered from gas electron multiplier (GEM) detector for diagnostic of plasma impurities. Measured execution times are estimates of achievable times for future and more complex algorithms. The work covers usage of Intel Xeon and Intel Xeon Phi - high-performance computing (HPC) devices as a possible replacement for FPGA with highlighted advantages and disadvantages. Results show that less than 10 ms feedback loop can be obtained with the usage of 25% hardware resources in Intel Xeon or 10% resources in Intel Xeon Phi which leaves space for future increase of algorithms complexity. Moreover, this work contains a simplified overview of basic problems in actual measurement systems for diagnostic of plasma impurities, and emerging trends in developed solutions.

Efficient Transfer of C++ Objects on Intel Xeon Phi KNC in Offload Mode

Hanousek V., Oberhuber T.

Computer Methods in Materials Science

2017

Vol. 17, No. 2

94--100

Intel Xeon Phi KNC is a modern coprocessor designed for the high performance computing. In this paper we describe efficient method for transferring C++ objects in the Offloading mode. Our aim is to get consistent interface with NVidia CUDA framework in Template Numerical Library (TNL). As working example we use this library and the heat equation problem to demonstrate efficiency of implementation on Intel Xeon Phi and compare CPU with this coprocessor.

Intel Xeon Phi jest nowoczesnym koprocesorem prze naczonym do obliczeń wysokiej wydajności w dużej mierze podobnym do układów GPU NVidia. TNL (Template Numerical Library) jest biblioteką dostarczającą abstrakcyjną warstwę umożliwiającą dostęp do wielordzeniowych procesorów' CPU i GPU przez solwery numeryczne. Naszym celem jest stworzerzenie interfejsu dla koprocesora Intel Xeon Phi zgodnego z Nvic CUDA w TNL. W pracy przedstawiono wydajną metodę kopiowania bitowego obiektów języka C++, podobną do tej zaimplementowanej w NVidia CUDA z wykorzystaniem rozszerzerzenia offload języka C++. Jako przykład wykorzystano rozwiązanie problemu przewodzenia cieplnego w celu demonstracji efektywności implementacji opartej o Intel Xeon Phi Knights Comer oraz porównanie obliczeń CPU z koprocesorem.