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FPGA implementation of procedures for video quality assessment

Wielgosz M., Karwatowski M., Pietron M., Wiatr K.

Computer Science

2018

Vol. 19 (3)

279--305

The video resolutions used in a variety of media are constantly rising. While manufacturers struggle to perfect their screens, it is also important to ensure the high quality of the displayed image. Overall quality can be measured using a Mean Opinion Score (MOS). Video quality can be affected by miscellaneous artifacts appearing at every stage of video creation and transmission. In this paper, we present a solution to calculate four distinct video quality metrics that can be applied to a real-time video quality assessment system. Our assessment module is capable of processing 8K resolution in real time set at a level of 30 frames per second. The throughput of 2.19 GB/s surpasses the performance of pure software solutions. The module was created using a high-level language to concentrate on architectural optimization.

FPGA implementation of H.264 CAVLC decoder using High-Level Synthesis

Cichoń S., Gorgoń M.

Image Processing & Communications

2017

Vol. 22, no. 2

21--26

CONTEXT ADAPTIVE VARIABLE LENGTH CODING (CAVLC) is a method designed for coding residual pixel data after transform and quantization, in which different codes with variable length are chosen based on recently coded coefficients. Coded bitstream can be stored or transmitted. This method is optional in widely adopted H.264 video coding standard. The entire algorithm is a complex one, and also difficult to implement efficiently in FPGA, due to data dependency. When the complexity of the RTL implementation rises, it impacts the duration and costs of development. Therefore, usage of High Level Synthesis (HLS) may be beneficial with these types of projects. In this paper first known to authors implementation of CAVLC and Exp-Golomb decoders for H.264 intra decoder in Impulse C language will be presented and compared with other implementations. Proposed solution is able to decode more then 720p@40fps with FPGA module clock at 166MHz.