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1 International Journal of Microelectronics and Computer Science

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The architecture of a low phase noise low power Delta-Sigma Fractional-N synthesizer

Siwiec Krzysztof, Pleskacz Witold A.

International Journal of Microelectronics and Computer Science

2018

Vol. 9, nr 4

161--166

In this paper a new Delta Sigma Fractional N synthesizer architecture is presented. The synthesizer achieves low fractional spurs and quantization noise, which relaxes the trade-off between PLL bandwidth and phase noise. The proposed architecture is based on two delay lines, which are used to compensate the phase error resulting from fractional synthesis. Additionally, dedicated control and calibration circuitry is described. The synthesizer has been implemented in standard 130 nm CMOS technology, occupies 0.1S4 mm² silicon area and dissipates 3.6 mW of power from 1.2 V supply. Measurements show that the presented architecture achieves 30 dB phase noise reduction in comparison with a standard Delta Sigma Fractional N synthesizer. The integrated rms jitter is 2.76 ps and worst case fractional spur is -52 dBc.